公开(公告)号：US06972248B2

公开(公告)日：2005-12-06

申请号：US10709591

申请日：2004-05-17

申请人： Sweehan J. H. Yang ,  Kuo-Chien Wu ,  Shih-Fan Kuan

发明人： Sweehan J. H. Yang ,  Kuo-Chien Wu ,  Shih-Fan Kuan

IPC分类号： H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/76

CPC分类号： H01L21/76816 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/78

摘要： A method of fabricating a semiconductor device. A stack gate structure having a cap layer thereon and a first dielectric layer having a top surface that exposes the cap layer are formed on a substrate. A buffer layer is formed to cover the dielectric layer and the cap layers in a first region of the substrate. A portion of the cap layers in a second region of the substrate are removed so that the cap layers have a thickness smaller than or equal to the buffer layer. A second dielectric layer is formed over the substrate. A portion of the second dielectric layer and the underlying the buffer layer and the first dielectric layer are etched to form a bit line contact opening. In the meantime, a portion of the second dielectric layer and the underlying cap layer are etched to form a gate contact opening.

公开(公告)号：US06943099B2

公开(公告)日：2005-09-13

申请号：US10768070

申请日：2004-02-02

申请人： Shih-Fan Kuan ,  Kuo-Chien Wu

发明人： Shih-Fan Kuan ,  Kuo-Chien Wu

IPC分类号： H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8242

CPC分类号： H01L29/6656 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10891

摘要： A method for manufacturing a gate structure has the steps of providing a substrate; forming a conducting layer on the substrate; forming a metal layer on the conducting layer; forming a patterned first protective layer on the metal layer, the protective layer having a side surface; partially removing the side surface of the first protective layer to form a first gate element having a first gate pattern; transferring the first gate pattern to the metal layer to form a second gate element; conformally forming a second protective layer on the first gate element, the second gate element and the conducting layer, causing a second gate pattern; and transferring the second gate pattern to the conducting layer to form a third gate element.

摘要翻译： 制造栅极结构的方法具有提供基板的步骤; 在基板上形成导电层; 在导电层上形成金属层; 在所述金属层上形成图案化的第一保护层，所述保护层具有侧表面; 部分地去除第一保护层的侧表面以形成具有第一栅极图案的第一栅极元件; 将所述第一栅极图案转移到所述金属层以形成第二栅极元件; 在第一栅极元件，第二栅极元件和导电层上保形地形成第二保护层，引起第二栅极图案; 以及将所述第二栅极图案转移到所述导电层以形成第三栅极元件。

公开(公告)号：US20050026409A1

公开(公告)日：2005-02-03

申请号：US10628507

申请日：2003-07-29

申请人： Kuo-Chien Wu ,  Shih-Fan Kuan

发明人： Kuo-Chien Wu ,  Shih-Fan Kuan

IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L21/8242

CPC分类号： H01L27/10888 ,  H01L27/10885

摘要： Disclosed is a method for forming bit line and bit line contact structure. Based on a semi-finished structure with a poly plug filled in a contact window, the method of the Invention comprises steps of removing some of the oxide layer so that the plug protrudes, oxidizing the exposed region of the protruding portion of the plug, removing the oxidized portion of the plug, forming a first dielectric layer to the upper surface of the resultant structure, wherein the upper surface of the plug is exposed, forming a second dielectric layer to the upper surface of the first dielectric layer including the upper surface of the plug, forming photoresist on the second dielectric layer, then performing exposing, developing and etching to form a trench of a predetermined pattern, and filling metal into the trench to form a bit line.

摘要翻译： 公开了一种用于形成位线和位线接触结构的方法。 基于填充在接触窗口中的具有多芯塞的半成品结构，本发明的方法包括以下步骤：去除一些氧化物层，使得插头突出，氧化插头的突出部分的暴露区域，去除 所述插头的氧化部分形成到所述结构的上表面的第一电介质层，其中所述插头的上表面被暴露，在所述第一电介质层的上表面形成第二电介质层，所述第二电介质层包括： 在第二电介质层上形成光致抗蚀剂，然后进行曝光，显影和蚀刻以形成预定图案的沟槽，并将金属填充到沟槽中以形成位线。

公开(公告)号：US20050275109A1

公开(公告)日：2005-12-15

申请号：US11160594

申请日：2005-06-30

申请人： Shih-Fan Kuan ,  Kuo-Chien Wu

发明人： Shih-Fan Kuan ,  Kuo-Chien Wu

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/8239 ,  H01L23/485 ,  H01L27/105 ,  H01L23/52

CPC分类号： H01L21/76897 ,  H01L21/76804 ,  H01L23/485 ,  H01L27/105 ,  H01L27/1052 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and method of manufacturing the same are disclosed. A conductive structure, spacers and a dielectric layer are formed on a substrate. Thereafter, a portion of the cap layer, a portion of the spacers and a portion of the dielectric layer of the conductive structure are removed to form a funnel-shaped opening. The shoulder section of the conductive layer exposed by the funnel-shaped opening is removed to form a shoulder recess. A liner layer is formed on the sidewall of the funnel-shaped opening and then a bottom plug is formed inside the funnel-shaped opening. Another dielectric layer is formed over the substrate. A top plug is formed in the dielectric layer such that the top plug and the bottom plug are electrically connected. Finally, a wire line is formed over the substrate.

摘要翻译： 公开了半导体器件及其制造方法。 在衬底上形成导电结构，间隔物和电介质层。 此后，去除盖层的一部分，间隔物的一部分和导电结构的电介质层的一部分以形成漏斗形开口。 由漏斗形开口暴露的导电层的肩部被去除以形成肩部凹陷。 衬套层形成在漏斗形开口的侧壁上，然后在漏斗形开口内部形成底部塞子。 在衬底上形成另一介电层。 在电介质层中形成顶塞，使得顶塞和底塞电连接。 最后，在衬底上形成有线线。

公开(公告)号：US20050176244A1

公开(公告)日：2005-08-11

申请号：US10772380

申请日：2004-02-06

申请人： Shih-Fan Kuan ,  Kuo-Chien Wu

发明人： Shih-Fan Kuan ,  Kuo-Chien Wu

IPC分类号： H01L21/28 ,  H01L21/44 ,  H01L21/60 ,  H01L21/8242 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L21/76897 ,  H01L21/28114 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/42376 ,  H01L29/4933

摘要： A method for manufacturing a gate structure of a memory comprises the steps of providing a substrate; forming a plurality of gates on the surface of said substrate, each gate having a metal layer; forming a photoresist layer of a predetermined pattern on the surface of said substrate and on said gates to selectively form an opening between two of said gates; removing a portion of said metal layer in said gate adjacent to said opening; removing said photoresist layer; and forming an insulating layer on the sidewalls of said gate.

摘要翻译： 一种用于制造存储器的栅极结构的方法，包括以下步骤：提供衬底; 在所述衬底的表面上形成多个栅极，每个栅极具有金属层; 在所述基板的表面和所述栅极上形成预定图案的光致抗蚀剂层，以选择性地形成两个所述栅极之间的开口; 去除邻近所述开口的所述门中的所述金属层的一部分; 去除所述光致抗蚀剂层; 以及在所述栅极的侧壁上形成绝缘层。

公开(公告)号：US06991978B2

公开(公告)日：2006-01-31

申请号：US10858032

申请日：2004-06-01

申请人： Shih-Fan Kuan ,  Kuo-Chien Wu

发明人： Shih-Fan Kuan ,  Kuo-Chien Wu

IPC分类号： H01L29/72

CPC分类号： H01L27/10891 ,  H01L21/28114 ,  H01L21/76897 ,  H01L27/10873 ,  H01L27/10888 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/6656

摘要： A word line structure with a single-sided partially recessed gate structure. The word line structure includes a gate structure, a first gate spacer, and a second gate spacer. The gate structure includes a gate dielectric layer, a first gate layer, a second gate layer, and a gate capping layer and has a recess region adjacent to one of opposing sidewalls of the second gate layer. The first gate spacer is disposed over opposing sidewalls of the gate dielectric layer and the first gate layer. The second gate spacer is disposed over opposing sidewalls of the gate structure and covers the first gate spacer. A method for forming a word line structure with a single-sided partially recessed gate structure is also disclosed.

摘要翻译： 具有单面部分凹陷栅结构的字线结构。 字线结构包括栅极结构，第一栅极隔离物和第二栅极间隔物。 栅极结构包括栅极介电层，第一栅极层，第二栅极层和栅极覆盖层，并且具有与第二栅极层的相对侧壁之一相邻的凹陷区域。 第一栅极间隔物设置在栅极介电层和第一栅极层的相对侧壁上。 第二栅极间隔物设置在栅极结构的相对侧壁上并且覆盖第一栅极间隔物。 还公开了一种用于形成具有单面部分凹陷栅极结构的字线结构的方法。

公开(公告)号：US20050202666A1

公开(公告)日：2005-09-15

申请号：US10709591

申请日：2004-05-17

申请人： Sweehan J.H. Yang ,  Kuo-Chien Wu ,  Shih-Fan Kuan

发明人： Sweehan J.H. Yang ,  Kuo-Chien Wu ,  Shih-Fan Kuan

IPC分类号： H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/76

CPC分类号： H01L21/76816 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/78

摘要： A method of fabricating a semiconductor device. A stack gate structure having a cap layer thereon and a first dielectric layer having a top surface that exposes the cap layer are formed on a substrate. A buffer layer is formed to cover the dielectric layer and the cap layers in a first region of the substrate. A portion of the cap layers in a second region of the substrate are removed so that the cap layers have a thickness smaller than or equal to the buffer layer. A second dielectric layer is formed over the substrate. A portion of the second dielectric layer and the underlying the buffer layer and the first dielectric layer are etched to form a bit line contact opening. In the meantime, a portion of the second dielectric layer and the underlying cap layer are etched to form a gate contact opening.

摘要翻译： 一种制造半导体器件的方法。 在基板上形成具有盖层的堆叠栅极结构和具有暴露盖层的顶表面的第一介电层。 形成缓冲层以覆盖基板的第一区域中的电介质层和盖层。 去除衬底的第二区域中的一部分盖层，使得盖层具有小于或等于缓冲层的厚度。 第二介质层形成在衬底上。 第二介电层的一部分和缓冲层下面的第一介电层被蚀刻以形成位线接触开口。 同时，第二电介质层的一部分和下面的盖层被蚀刻以形成栅极接触开口。

公开(公告)号：US20050003307A1

公开(公告)日：2005-01-06

申请号：US10743135

申请日：2003-12-23

申请人： Shih-Fan Kuan ,  Kuo-Chien Wu

发明人： Shih-Fan Kuan ,  Kuo-Chien Wu

IPC分类号： G03F7/00 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242

CPC分类号： H01L21/76897 ,  H01L21/76804 ,  H01L27/10888

摘要： A method for forming DRAM cell bit-line contact is provided. First a dielectric layer is formed on a substrate on which a plurality of control gates has already been formed, and then a patterned photoresist defining a first aperture is formed thereon. Afterwards, through the patterned photoresist the dielectric layer is etched away to expose the substrate there beneath to form the bit-line contact window. Thereafter the bit-line contact windows are filled with a conductive material to form the bit-line contact. Finally, a conductor layer is formed on a previously formed isolation layer, which has a second aperture and the partially exposed bit-line contact, to fill the second aperture.

摘要翻译： 提供了一种用于形成DRAM单元位线接触的方法。 首先，在其上已经形成有多个控制栅极的基板上形成介电层，然后在其上形成限定第一孔的图案化光致抗蚀剂。 之后，通过图案化的光致抗蚀剂，电介质层被蚀刻掉以暴露其下面的衬底以形成位线接触窗口。 此后，位线接触窗口填充有导电材料以形成位线接触。 最后，导体层形成在预先形成的隔离层上，该隔离层具有第二孔和部分暴露的位线接触以填充第二孔。

公开(公告)号：US07358576B2

公开(公告)日：2008-04-15

申请号：US11246428

申请日：2005-10-07

申请人： Shih-Fan Kuan ,  Kuo-Chien Wu

发明人： Shih-Fan Kuan ,  Kuo-Chien Wu

IPC分类号： H01L29/72

CPC分类号： H01L27/10891 ,  H01L21/28114 ,  H01L21/76897 ,  H01L27/10873 ,  H01L27/10888 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/6656

摘要： A word line structure with a single-sided partially recessed gate structure. The word line structure includes a gate structure, a first gate spacer, and a second gate spacer. The gate structure includes a gate dielectric layer, a first gate layer, a second gate layer, and a gate capping layer and has a recess region adjacent to one of opposing sidewalls of the second gate layer. The first gate spacer is disposed over opposing sidewalls of the gate dielectric layer and the first gate layer. The second gate spacer is disposed over opposing sidewalls of the gate structure and covers the first gate spacer. A method for forming a word line structure with a single-sided partially recessed gate structure is also disclosed.

摘要翻译： 具有单面部分凹陷栅结构的字线结构。 字线结构包括栅极结构，第一栅极隔离物和第二栅极间隔物。 栅极结构包括栅极介电层，第一栅极层，第二栅极层和栅极覆盖层，并且具有与第二栅极层的相对侧壁之一相邻的凹陷区域。 第一栅极间隔物设置在栅极介电层和第一栅极层的相对侧壁上。 第二栅极间隔物设置在栅极结构的相对侧壁上并且覆盖第一栅极间隔物。 还公开了一种用于形成具有单面部分凹陷栅极结构的字线结构的方法。

公开(公告)号：US20050170624A1

公开(公告)日：2005-08-04

申请号：US10768070

申请日：2004-02-02

申请人： Shih-Fan Kuan ,  Kuo-Chien Wu

发明人： Shih-Fan Kuan ,  Kuo-Chien Wu

IPC分类号： H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8242

CPC分类号： H01L29/6656 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10891

摘要： A method for manufacturing a gate structure has the steps of providing a substrate; forming a conducting layer on the substrate; forming a metal layer on the conducting layer; forming a patterned first protective layer on the metal layer, the protective layer having a side surface; partially removing the side surface of the first protective layer to form a first gate element having a first gate pattern; transferring the first gate pattern to the metal layer to form a second gate element; conformally forming a second protective layer on the first gate element, the second gate element and the conducting layer, causing a second gate pattern; and transferring the second gate pattern to the conducting layer to form a third gate element.

摘要翻译： 制造栅极结构的方法具有提供基板的步骤; 在基板上形成导电层; 在导电层上形成金属层; 在所述金属层上形成图案化的第一保护层，所述保护层具有侧表面; 部分地去除第一保护层的侧表面以形成具有第一栅极图案的第一栅极元件; 将所述第一栅极图案转移到所述金属层以形成第二栅极元件; 在第一栅极元件，第二栅极元件和导电层上保形地形成第二保护层，引起第二栅极图案; 以及将所述第二栅极图案转移到所述导电层以形成第三栅极元件。