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    CMOS Image Sensor Chips with Stacked Scheme and Methods for Forming the Same
    4.
    发明申请
    CMOS Image Sensor Chips with Stacked Scheme and Methods for Forming the Same 审中-公开
    具有堆叠方案的CMOS图像传感器芯片及其形成方法

    公开(公告)号：US20140042298A1

    公开(公告)日：2014-02-13

    申请号：US13571099

    申请日：2012-08-09

    申请人： Meng-Hsun Wan ,  Szu-Ying Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu

    发明人： Meng-Hsun Wan ,  Szu-Ying Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu

    IPC分类号： H01L27/146 ,  H01L31/18 ,  H01L27/148

    CPC分类号： H01L27/14634 ,  H01L27/1464 ,  H01L27/1469

    摘要： A device includes an image sensor chip having an image sensor therein. A read-out chip is underlying and bonded to the image sensor chip, wherein the read-out chip includes a logic device selected from the group consisting essentially of a reset transistor, a source follower, a row selector, and combinations thereof therein. The logic device and the image sensor are electrically coupled to each other, and are parts of a same pixel unit. A peripheral circuit chip is underlying and bonded to the read-out chip, wherein the peripheral circuit chip includes a logic circuit.

    摘要翻译： 一种装置包括其中具有图像传感器的图像传感器芯片。 读出芯片是底层的并且结合到图像传感器芯片上，其中读出芯片包括从基本上由复位晶体管，源极跟随器，行选择器及其组合组成的组中选择的逻辑器件。 逻辑器件和图像传感器彼此电耦合，并且是相同像素单元的部分。 外围电路芯片在下面并与读出的芯片结合，其中外围电路芯片包括一个逻辑电路。

    CMOS image sensor chips with stacked scheme and methods for forming the same
    5.
    发明授权
    CMOS image sensor chips with stacked scheme and methods for forming the same 有权
    具有堆叠方案的CMOS图像传感器芯片及其形成方法

    公开(公告)号：US08957358B2

    公开(公告)日：2015-02-17

    申请号：US13571184

    申请日：2012-08-09

    申请人： Meng-Hsun Wan ,  Szu-Ying Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu

    发明人： Meng-Hsun Wan ,  Szu-Ying Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu

    IPC分类号： H01L27/146

    CPC分类号： H01L27/14634 ,  H01L27/14609 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/1469

    摘要： A device includes an image sensor chip including an image sensor therein. A read-out chip is underlying and bonded to the image sensor chip. The read-out chip includes a logic device selected from the group consisting essentially of a reset transistor, a source follower, a row selector, and combinations thereof therein. The logic device and the image sensor are electrically coupled to each other, and are parts of a same pixel unit. A peripheral circuit chip is underlying and bonded to the read-out chip. The peripheral circuit chip includes a logic circuit, a through via penetrating through a semiconductor substrate of the peripheral circuit chip, and an electrical connector at a bottom surface of the peripheral circuit chip. The electrical connector is electrically coupled to the logic circuit in the peripheral circuit chip through the through via.

    摘要翻译： 一种设备包括其中包括图像传感器的图像传感器芯片。 一个读出的芯片是底层的，并粘贴到图像传感器芯片上。 读出芯片包括从基本上由复位晶体管，源极跟随器，行选择器及其组合组成的组中选择的逻辑器件。 逻辑器件和图像传感器彼此电耦合，并且是相同像素单元的部分。 外围电路芯片是底层的，并与读出的芯片结合。 外围电路芯片包括逻辑电路，穿透外围电路芯片的半导体衬底的贯通孔以及外围电路芯片底面的电连接器。 电连接器通过通孔电耦合到外围电路芯片中的逻辑电路。

    CMOS Image Sensor Chips with Stacked Scheme and Methods for Forming the Same
    6.
    发明申请
    CMOS Image Sensor Chips with Stacked Scheme and Methods for Forming the Same 有权
    具有堆叠方案的CMOS图像传感器芯片及其形成方法

    公开(公告)号：US20140042299A1

    公开(公告)日：2014-02-13

    申请号：US13571184

    申请日：2012-08-09

    申请人： Meng-Hsun Wan ,  Szu-Ying Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu

    发明人： Meng-Hsun Wan ,  Szu-Ying Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu

    IPC分类号： H01L27/146 ,  H01L27/148 ,  H01L31/18

    CPC分类号： H01L27/14634 ,  H01L27/14609 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/1469

    摘要： A device includes an image sensor chip including an image sensor therein. A read-out chip is underlying and bonded to the image sensor chip. The read-out chip includes a logic device selected from the group consisting essentially of a reset transistor, a source follower, a row selector, and combinations thereof therein. The logic device and the image sensor are electrically coupled to each other, and are parts of a same pixel unit. A peripheral circuit chip is underlying and bonded to the read-out chip. The peripheral circuit chip includes a logic circuit, a through via penetrating through a semiconductor substrate of the peripheral circuit chip, and an electrical connector at a bottom surface of the peripheral circuit chip. The electrical connector is electrically coupled to the logic circuit in the peripheral circuit chip through the through via.

    摘要翻译： 一种设备包括其中包括图像传感器的图像传感器芯片。 一个读出的芯片是底层的，并粘贴到图像传感器芯片上。 读出芯片包括从基本上由复位晶体管，源极跟随器，行选择器及其组合组成的组中选择的逻辑器件。 逻辑器件和图像传感器彼此电耦合，并且是相同像素单元的部分。 外围电路芯片是底层的，并与读出的芯片结合。 外围电路芯片包括逻辑电路，穿透外围电路芯片的半导体衬底的贯通孔以及外围电路芯片底面的电连接器。 电连接器通过通孔电耦合到外围电路芯片中的逻辑电路。

    Method and apparatus for image sensor packaging
    7.
    发明授权
    Method and apparatus for image sensor packaging 有权
    图像传感器封装的方法和装置

    公开(公告)号：US08710607B2

    公开(公告)日：2014-04-29

    申请号：US13547269

    申请日：2012-07-12

    申请人： Szu-Ying Chen ,  Tzu-Jui Wang ,  Dun-Nian Yaung ,  Jen-Cheng Liu

    发明人： Szu-Ying Chen ,  Tzu-Jui Wang ,  Dun-Nian Yaung ,  Jen-Cheng Liu

    IPC分类号： H01L31/18 ,  H01L31/02 ,  H01L27/146

    CPC分类号： H01L27/14636 ,  H01L24/06 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/1464 ,  H01L2224/0603 ,  H01L2224/06131 ,  H01L2924/12043

    摘要： Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a BSI sensor device with an application specific integrated circuit (ASIC) are disclosed. A bond pad array may be formed in a bond pad area of a BSI sensor where the bond pad array comprises a plurality of bond pads electrically interconnected, wherein each bond pad of the bond pad array is of a small size which can reduce the dishing effect of a big bond pad. The plurality of bond pads of a bond pad array may be interconnected at the same layer of the pad or at a different metal layer. The BSI sensor may be bonded to an ASIC in a face-to-face fashion where the bond pad arrays are aligned and bonded together.

    摘要翻译： 公开了用专用集成电路（ASIC）封装背面照明（BSI）图像传感器或BSI传感器装置的方法和装置。 接合焊盘阵列可以形成在BSI传感器的接合焊盘区域中，其中接合焊盘阵列包括电互连的多个接合焊盘，其中接合焊盘阵列的每个接合焊盘是小尺寸的，这可以减小凹陷效应 的大债券垫。 接合焊盘阵列的多个接合焊盘可以在焊盘的相同层处或在不同的金属层处互连。 BSI传感器可以以面对面的方式结合到ASIC，其中接合焊盘阵列对准并结合在一起。