公开(公告)号：US20190164751A1

公开(公告)日：2019-05-30

申请号：US15880389

申请日：2018-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chien CHI ,  Hsiao-Kuan WEI ,  Hung-Wen SU ,  Pei-Hsuan LEE ,  Hsin-Yun HSU ,  Jui-Fen CHIEN

IPC: H01L21/02 ,  H01L21/28 ,  H01L27/092 ,  H01L21/20 ,  H01L21/324 ,  H01L29/423 ,  H01L29/49 ,  H01L21/762 ,  H01L29/66

Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

公开(公告)号：US20190123175A1

公开(公告)日：2019-04-25

申请号：US15901992

申请日：2018-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yun HSU ,  Hsiao-Kuan WEI

IPC: H01L29/66 ,  H01L21/321 ,  H01L21/28 ,  H01L29/78 ,  H01L29/49 ,  H01L29/423

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a fin structure protruding therefrom, an insulating layer is over the substrate to cover the fin structure, a gate structure in the insulating layer and over the fin structure, and source and drain features covered by the insulating layer and over the fin structure on opposing sidewall surfaces of the gate structure. The gate structure includes a gate electrode layer, a conductive sealing layer covering the gate electrode layer, and a gate dielectric layer between the fin structure and the gate electrode layer and surrounding the gate electrode layer and the conductive sealing layer. The gate electrode layer has a material removal rate that is higher than the material removal rate of the conductive sealing layer in a chemical mechanical polishing process.

公开(公告)号：US20190385855A1

公开(公告)日：2019-12-19

申请号：US16008321

申请日：2018-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Fen CHIEN ,  Chih-Hsiang FAN ,  Hsiao-Kuan WEI ,  Pohan KUNG ,  Hsien-Ming LEE

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/321 ,  H01L29/66

Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a gate dielectric layer over a substrate. The method also includes depositing a first p-type work function tuning layer over the gate dielectric layer using a first atomic layer deposition (ALD) process with an inorganic precursor. The method further includes forming a second p-type work function tuning layer on the first p-type work function tuning layer using a second atomic layer deposition (ALD) process with an organic precursor. In addition, the method includes forming an n-type work function metal layer over the second p-type work function tuning layer.

公开(公告)号：US20190334007A1

公开(公告)日：2019-10-31

申请号：US15964769

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yun HSU ,  Hsiao-Kuan WEI

IPC: H01L29/49 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer over a substrate. A first metal layer is formed in the first insulating layer and over the substrate. A silicon- and fluorine-containing barrier layer is formed between the first insulating layer and the first metal layer and between the substrate and the first metal layer. The silicon- and fluorine-containing barrier layer has a silicon content in a range from about 5% to about 20%.

公开(公告)号：US20190096680A1

公开(公告)日：2019-03-28

申请号：US15824474

申请日：2017-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Kuan WEI ,  Hsien-Ming LEE ,  Chin-You HSU ,  Hsin-Yun HSU ,  Pin-Hsuan YEH

IPC: H01L21/28 ,  H01L29/40 ,  H01L21/285 ,  H01L29/49 ,  H01L21/3213 ,  H01L29/51

Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.