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    Method of manufacturing a semiconductor device and a semiconductor device
    3.
    发明授权
    Method of manufacturing a semiconductor device and a semiconductor device 有权

    公开(公告)号：US10211217B2

    公开(公告)日：2019-02-19

    申请号：US15627726

    申请日：2017-06-20

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Yun-Chi Wu ,  Yu-Wen Tseng

    IPC分类号： H01L27/1157 ,  H01L27/12 ,  H01L29/51 ,  H01L29/66

    摘要： A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.

    Non-volatile memory device
    4.
    发明授权
    Non-volatile memory device 有权

    公开(公告)号：US11342025B2

    公开(公告)日：2022-05-24

    申请号：US16933718

    申请日：2020-07-20

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Yu-Wen Tseng ,  Tsung-Yu Yang ,  Chung-Jen Huang

    IPC分类号： G11C16/00 ,  G11C16/10 ,  G11C16/04 ,  H01L27/11521 ,  G11C16/14 ,  H01L27/11526 ,  H01L29/788 ,  H01L27/11524 ,  H01L29/423

    摘要： A memory unit includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, floating gate structures select gates, a common source and drains. The common source is disposed in the substrate, and the erase gate structure is disposed on the common source. The floating gate structures protrude from recesses of the substrate at two opposite sides of the erase gate structure. A method for controlling the memory unit includes applying an erase gate programming voltage on the erase gate structure, applying a control gate programming voltage on the common source, applying a bit line programming voltage on the drains, and applying word line programming voltage on the select gates, in which the control gate programming voltage is greater than the erase gate programming voltage.

    Method of manufacturing a semiconductor device and a semiconductor device
    5.
    发明授权
    Method of manufacturing a semiconductor device and a semiconductor device 有权

    公开(公告)号：US10665602B2

    公开(公告)日：2020-05-26

    申请号：US16198100

    申请日：2018-11-21

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Yun-Chi Wu ,  Yu-Wen Tseng

    IPC分类号： H01L29/423 ,  H01L27/1157 ,  H01L27/12 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/792 ,  H01L29/775 ,  H01L27/11568

    摘要： A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.

    Method of manufacturing a semiconductor device and a semiconductor device
    6.
    发明授权
    Method of manufacturing a semiconductor device and a semiconductor device 有权

    公开(公告)号：US11031412B2

    公开(公告)日：2021-06-08

    申请号：US16859155

    申请日：2020-04-27

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Yun-Chi Wu ,  Yu-Wen Tseng

    IPC分类号： H01L27/1157 ,  H01L29/423 ,  H01L27/12 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/792 ,  H01L29/775 ,  H01L27/11568

    摘要： A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.