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    Method for manufacturing embedded non-volatile memory
    3.
    发明授权
    Method for manufacturing embedded non-volatile memory 有权

    公开(公告)号：US10204917B2

    公开(公告)日：2019-02-12

    申请号：US15420232

    申请日：2017-01-31

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Tsung-Yu Yang ,  Chung-Jen Huang

    IPC分类号： H01L21/336 ,  H01L27/1157 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/423 ,  H01L29/792 ,  H01L27/11573

    摘要： In a method for manufacturing a semiconductor device, a cell well, a logic well and a high voltage well are formed in a first, a second and a third regions of a substrate. A first and a second stacked structures are formed on the first and second regions. A first and a second word line wells are formed in the cell well. First spacers are formed on sidewalls of the first and second stacked structures. A first gate oxide layer is formed on the third region and the first and second word line wells. A portion of the first stacked structure is removed to form a first and a second device structures. A second gate oxide layer is formed to cover the first, second and third regions. A first and a second word lines are formed adjacent to the first and second device structures.

    Non-volatile memory of semiconductor device and method for manufacturing the same
    4.
    发明授权
    Non-volatile memory of semiconductor device and method for manufacturing the same 有权

    公开(公告)号：US10170488B1

    公开(公告)日：2019-01-01

    申请号：US15865454

    申请日：2018-01-09

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Cheng-Bo Shu ,  Tsung-Yu Yang ,  Chung-Jen Huang

    IPC分类号： H01L21/00 ,  H01L27/11517 ,  H01L29/78 ,  H01L29/423 ,  H01L21/28 ,  H01L21/762

    摘要： A semiconductor device includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, a first floating gate structure, a second floating gate structure, a first word line, a common source, a second word line, a first spacer and a second spacer. The first floating gate structure and the second floating gate structure are recessed in the substrate at two opposite sides of the erase gate structure. The first word line and the second word line are respectively adjacent to the first floating gate structure and the second floating gate structure. The common source is disposed in the substrate under the erase gate structure. The first spacer and the second spacer are respectively disposed between the first floating gate structure and the first word line and between the second floating gate structure and the second word line.

    Handle wafer for high resistivity trap-rich SOI
    7.
    发明授权
    Handle wafer for high resistivity trap-rich SOI 有权
    处理高电阻阱富集SOI的晶圆

    公开(公告)号：US09269591B2

    公开(公告)日：2016-02-23

    申请号：US14222785

    申请日：2014-03-24

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Alex Kalnitsky ,  Chung-Long Chang ,  Yung-Chih Tsai ,  Tsung-Yu Yang ,  Keng-Yu Chen ,  Yong-En Syu

    IPC分类号： H01L21/322 ,  H01L27/12 ,  H01L29/34

    CPC分类号： H01L21/3226 ,  H01L21/26506 ,  H01L21/304 ,  H01L21/3046 ,  H01L21/32105 ,  H01L21/7624 ,  H01L27/1203 ,  H01L29/34

    摘要： The present disclosure relates to a silicon-on-insulator (SOI) substrate having a trap-rich layer, with crystal defects, which is disposed within a handle wafer, and an associated method of formation. In some embodiments, the SOI substrate has a handle wafer. A trap-rich layer, having a plurality of crystal defects that act to trap carriers, is disposed within the handle wafer at a position abutting a top surface of the handle wafer. An insulating layer is disposed onto the handle wafer. The insulating layer has a first side abutting the top surface of the handle wafer and an opposing second side abutting a thin layer of active silicon. By forming the trap-rich layer within the handle wafer, fabrication costs associated with depositing a trap-rich material (e.g., polysilicon) onto a handle wafer are reduced and thermal instability issues are prevented.

    摘要翻译： 本公开内容涉及具有富集陷阱层的绝缘体上硅（SOI）衬底，其具有设置在处理晶片内的晶体缺陷以及相关联的形成方法。 在一些实施例中，SOI衬底具有处理晶片。 在与处理晶片的顶表面相邻的位置处，在处理晶片内设置具有多个用于捕获载流子的晶体缺陷的富含阱的层。 绝缘层设置在手柄晶片上。 绝缘层具有邻接手柄晶片的顶表面的第一侧和与活性硅薄层邻接的相对的第二侧。 通过在处理晶片内形成富含阱的层，减少了将富含陷阱的材料（例如多晶硅）沉积到处理晶片上的制造成本，并防止了热不稳定性问题。