公开(公告)号：US20220077384A1

公开(公告)日：2022-03-10

申请号：US17525927

申请日：2021-11-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Ya-Jui TSOU ,  Zong-You LUO ,  Chee-Wee LIU ,  Shao-Yu LIN ,  Liang-Chor CHUNG ,  Chih-Lin WANG

IPC分类号： H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16

摘要： A magnetoresistive memory device includes a memory stack, a spin-orbit-torque (SOT) layer, and a free layer. The memory stack includes a pinned layer, a spacer layer over the pinned layer, a reference layer over the spacer layer, and a tunnel barrier layer over the reference layer. The SOT layer has a top surface substantially coplanar with a top surface of the tunnel barrier layer of the memory stack. The free layer interconnects the SOT layer and the tunnel barrier layer.

公开(公告)号：US20230363287A1

公开(公告)日：2023-11-09

申请号：US18353569

申请日：2023-07-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Ya-Jui TSOU ,  Zong-You LUO ,  Chee-Wee LIU ,  Shao-Yu LIN ,  Liang-Chor CHUNG ,  Chih-Lin WANG

IPC分类号： H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01

CPC分类号： H10N50/80 ,  G11C11/161 ,  H10B61/00 ,  H10N50/01

摘要： A method includes forming a memory stack over a substrate. A dielectric layer is deposited to cover the memory stack. An opening is formed in the dielectric layer. The opening does not expose the memory stack. A spin-orbit-torque (SOT) layer is formed in the opening. A free layer is formed over the dielectric layer to interconnect the memory stack and the SOT layer.

公开(公告)号：US20220358980A1

公开(公告)日：2022-11-10

申请号：US17871983

申请日：2022-07-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Zong-You LUO ,  Ya-Jui TSOU ,  Chee-Wee LIU ,  Shao-Yu LIN ,  Liang-Chor CHUNG ,  Chih-Lin WANG

IPC分类号： G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02

摘要： A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.

公开(公告)号：US20210082482A1

公开(公告)日：2021-03-18

申请号：US16572329

申请日：2019-09-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Zong-You LUO ,  Ya-Jui TSOU ,  Chee-Wee LIU ,  Shao-Yu LIN ,  Liang-Chor CHUNG ,  Chih-Lin WANG

IPC分类号： G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

摘要： A magnetoresistive memory device includes a plurality of bottom conductive lines, a plurality of top conductive lines, a first memory cell, and a second memory cell. The top conductive lines are over the bottom conductive lines. The first memory cell is between the bottom conductive lines and the top conductive lines and includes a first magnetic tunnel junction (MTJ) stack. The second memory cell is adjacent the first memory cell and between the bottom conductive lines and the top conductive lines. The second memory cell includes a second MTJ stack, and a top surface of the second MTJ stack is higher than a top surface of the first MTJ stack.

公开(公告)号：US20230360686A1

公开(公告)日：2023-11-09

申请号：US18352872

申请日：2023-07-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Zong-You LUO ,  Ya-Jui TSOU ,  Chee-Wee LIU ,  Shao-Yu LIN ,  Liang-Chor CHUNG ,  Chih-Lin WANG

IPC分类号： G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC分类号： G11C11/161 ,  H10B61/00 ,  H10B61/20 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

摘要： A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.