公开(公告)号：US20230378266A1

公开(公告)日：2023-11-23

申请号：US18362778

申请日：2023-07-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Chung-En TSAI ,  Chia-Che CHUNG ,  Chee-Wee LIU ,  Fang-Liang LU ,  Yu-Shiang HUANG ,  Hung-Yu YEH ,  Chien-Te TU ,  Yi-Chun LIU

IPC分类号： H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/0673 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/0665 ,  H01L29/78618 ,  H01L29/78696

摘要： A device comprise a first semiconductor channel layer over a substrate, a second semiconductor channel layer over the first semiconductor channel layer, and source/drain epitaxial structures on opposite sides of the first semiconductor channel layer and opposite sides of the second semiconductor channel layer. A compressive strain in the second semiconductor channel layer is greater than a compressive strain in the first semiconductor channel layer. The source/drain epitaxial structures each comprise a first region interfacing the first semiconductor channel layer and a second region interfacing the second semiconductor channel layer, and the first region has a composition different from a composition of the second region.

公开(公告)号：US20230363287A1

公开(公告)日：2023-11-09

申请号：US18353569

申请日：2023-07-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Ya-Jui TSOU ,  Zong-You LUO ,  Chee-Wee LIU ,  Shao-Yu LIN ,  Liang-Chor CHUNG ,  Chih-Lin WANG

IPC分类号： H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01

CPC分类号： H10N50/80 ,  G11C11/161 ,  H10B61/00 ,  H10N50/01

摘要： A method includes forming a memory stack over a substrate. A dielectric layer is deposited to cover the memory stack. An opening is formed in the dielectric layer. The opening does not expose the memory stack. A spin-orbit-torque (SOT) layer is formed in the opening. A free layer is formed over the dielectric layer to interconnect the memory stack and the SOT layer.

公开(公告)号：US20220199630A1

公开(公告)日：2022-06-23

申请号：US17691879

申请日：2022-03-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Hung-Yu YE ,  Chung-Yi LIN ,  Yun-Ju PAN ,  Chee-Wee LIU

IPC分类号： H01L27/11 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L23/535 ,  H01L21/324 ,  H01L21/8238

摘要： A device includes a first horizontal-gate-all-around (HGAA) transistor, a second HGAA transistor, a first vertical-gate-all-around (VGAA) transistor, and a second VGAA transistor. The first HGAA transistor and the second HGAA transistor are adjacent to each other. The first VGAA transistor is over the first HGAA transistor. The second VGAA transistor is over the second HGAA transistor. A top surface of the first VGAA transistor is substantially coplanar with a top surface of the second VGAA transistor.

公开(公告)号：US20220149041A1

公开(公告)日：2022-05-12

申请号：US17585020

申请日：2022-01-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Chih-Hsiung HUANG ,  Chung-En TSAI ,  Chee-Wee LIU ,  Kun-Wa KUOK ,  Yi-Hsiu HSIAO

IPC分类号： H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/40

摘要： A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

公开(公告)号：US20210328012A1

公开(公告)日：2021-10-21

申请号：US16850974

申请日：2020-04-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Chung-En TSAI ,  Chia-Che CHUNG ,  Chee-Wee LIU ,  Fang-Liang LU ,  Yu-Shiang HUANG ,  Hung-Yu YEH ,  Chien-Te TU ,  Yi-Chun LIU

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L21/02 ,  H01L29/423

摘要： A method includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate; forming a dummy gate structure across the fin structure; etching portions of the fin structure to expose portions of the substrate; forming source/drain stressors over the exposed portions of the substrate; after forming the source/drain stressors, removing the dummy gate structure; after removing the dummy gate structure, removing the first semiconductor layers such that the second semiconductor layers are suspended between the source/drain stressors; and forming a gate structure to surround each of the suspended second semiconductor layers. The source/drain stressors each comprise a first source/drain layer and a second source/drain layer over the first source/drain layer. An atomic concentration of a Group IV element or a Group V element in the second source/drain layer is greater than that in the first source/drain layer.

公开(公告)号：US20190312132A1

公开(公告)日：2019-10-10

申请号：US16450637

申请日：2019-06-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： I-Hsieh WONG ,  Samuel C. PAN ,  Chee-Wee LIU ,  Huang-Siang LAN ,  Chung-En TSAI ,  Fang-Liang LU

IPC分类号： H01L29/66 ,  H01L29/165 ,  H01L21/324 ,  H01L29/786 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/08 ,  H01L21/02 ,  H01L21/268 ,  H01L21/306

摘要： A method of manufacturing a semiconductor device includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers on a substrate. The first and second semiconductor layers include first end portions on either side of a second portion along a length of the first and second semiconductor layers. The first and second semiconductor layers are formed of different materials. The second portion of the first semiconductor layers is removed to form spaces. A mask layer is formed over the second portion of an uppermost second semiconductor layer above the spaces. The first portions of first and second semiconductor layers are irradiated with radiation from a radiation source to cause material from the first portions of the first and second semiconductor layers to combine with each other.

公开(公告)号：US20230369331A1

公开(公告)日：2023-11-16

申请号：US18360416

申请日：2023-07-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Chih-Hsiung HUANG ,  Chung-En TSAI ,  Chee-Wee LIU ,  Kun-Wa KUOK ,  Yi-Hsiu HSIAO

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L27/092 ,  H01L21/823821 ,  H01L29/401 ,  H01L29/4966 ,  H01L21/823842 ,  H01L27/0924 ,  H01L21/28088 ,  H01L29/66545

摘要： A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

公开(公告)号：US20220358980A1

公开(公告)日：2022-11-10

申请号：US17871983

申请日：2022-07-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Zong-You LUO ,  Ya-Jui TSOU ,  Chee-Wee LIU ,  Shao-Yu LIN ,  Liang-Chor CHUNG ,  Chih-Lin WANG

IPC分类号： G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02

摘要： A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.

公开(公告)号：US20190164866A1

公开(公告)日：2019-05-30

申请号：US16166608

申请日：2018-10-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Jhih-Yang YAN ,  Fang-Liang LU ,  Chee-Wee LIU

IPC分类号： H01L23/367 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51 ,  H01L27/092 ,  H01L21/762 ,  H01L23/522 ,  H01L23/532

摘要： A device includes a non-insulator structure, a first ILD layer, a first thermal via, and a first electrical via. The first ILD is over the non-insulator structure. The first thermal via is through the first ILD layer and in contact with the non-insulator structure. The first electrical via is through the first ILD layer and in contact with the non-insulator structure. The first thermal via and the first electrical via have different materials and the same height.

公开(公告)号：US20190131403A1

公开(公告)日：2019-05-02

申请号：US15795519

申请日：2017-10-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

发明人： Fang-Liang LU ,  Chia-Che CHUNG ,  Yu-Jiun PENG ,  Chee-Wee LIU

IPC分类号： H01L29/10 ,  H01L29/66 ,  H01L29/78

摘要： A semiconductor device includes a substrate, a channel structure, and a gate structure. The channel structure is over the substrate and extends along a first direction, in which the channel structure has plurality of first portions and plurality of second portions alternately stacked, and a width of the first portions is smaller than that of the second portions in a second direction different from the first direction. The gate structure is disposed over the substrate and crossing the channel structure along the second direction, in which the gate structure is in contact with the first portions and the second portions.