公开(公告)号：US20190096674A1

公开(公告)日：2019-03-28

申请号：US16204023

申请日：2018-11-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Teng Liao ,  Yi-Wei Chiu ,  Chih Hsuan Cheng ,  Li-Te Hsu

IPC: H01L21/225 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78

Abstract: A method includes etching a semiconductor substrate to form a first trench and a second trench. A remaining portion of the semiconductor substrate is left between the first trench and the second trench as a semiconductor region. A doped dielectric layer is formed on sidewalls of the semiconductor region and over a top surface of the semiconductor region. The doped dielectric layer includes a dopant. The first trench and the second trench are filled with a dielectric material. An anneal is then performed, and a p-type dopant or an n-type dopant in the doped dielectric layer is diffused into the semiconductor region to form a diffused semiconductor region.

公开(公告)号：US12015085B2

公开(公告)日：2024-06-18

申请号：US17874281

申请日：2022-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yan-Ting Shen ,  Chia-Chi Yu ,  Chih-Teng Liao ,  Yu-Li Lin ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A semiconductor device includes a fin structure protruding from an isolation insulating layer disposed over a substrate and having a channel region, a source/drain region disposed over the substrate, a gate dielectric layer disposed on the channel region, and a gate electrode layer disposed on the gate dielectric layer. The gate electrode includes a lower portion below a level of a top of the channel region and above an upper surface of the isolation insulating layer, and a width of the lower portion is not constant.

公开(公告)号：US11171003B2

公开(公告)日：2021-11-09

申请号：US16204023

申请日：2018-11-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Teng Liao ,  Yi-Wei Chiu ,  Chih Hsuan Cheng ,  Li-Te Hsu

IPC: H01L21/8238 ,  H01L21/225 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes etching a semiconductor substrate to form a first trench and a second trench. A remaining portion of the semiconductor substrate is left between the first trench and the second trench as a semiconductor region. A doped dielectric layer is formed on sidewalls of the semiconductor region and over a top surface of the semiconductor region. The doped dielectric layer includes a dopant. The first trench and the second trench are filled with a dielectric material. An anneal is then performed, and a p-type dopant or an n-type dopant in the doped dielectric layer is diffused into the semiconductor region to form a diffused semiconductor region.

公开(公告)号：US10910223B2

公开(公告)日：2021-02-02

申请号：US15340636

申请日：2016-11-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Teng Liao ,  Yi-Wei Chiu ,  Chih Hsuan Cheng ,  Li-Te Hsu

IPC: H01L21/225 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes etching a semiconductor substrate to form a first trench and a second trench. A remaining portion of the semiconductor substrate is left between the first trench and the second trench as a semiconductor region. A doped dielectric layer is formed on sidewalls of the semiconductor region and over a top surface of the semiconductor region. The doped dielectric layer includes a dopant. The first trench and the second trench are filled with a dielectric material. An anneal is then performed, and a p-type dopant or an n-type dopant in the doped dielectric layer is diffused into the semiconductor region to form a diffused semiconductor region.

公开(公告)号：US20190006465A1

公开(公告)日：2019-01-03

申请号：US15665968

申请日：2017-08-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Teng Liao ,  Yi-Wei Chiu ,  Tzu-Chan Weng ,  Chih Hsuan Cheng

IPC: H01L29/08 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66

Abstract: A method includes etching a substrate to form a first semiconductor strip. A first dummy gate structure is formed over a first channel region of the first semiconductor strip. First and second recesses are etched in the first semiconductor strip on either side of a first dummy gate. An intermetallic doping film is formed in the first recess and the second recess. A dopant of the intermetallic doping film is diffused into the first semiconductor strip proximate the recesses. Source/drain regions are epitaxially grown in the recesses. A device includes semiconductor strips and a plurality of gate stacks. A first epitaxial source/drain region is interposed between a first two of the plurality of gate stacks. A first dopant diffusion area surrounds the first epitaxial source/drain region and has a first concentration of a first dopant greater than a second concentration of the first dopant outside the first dopant diffusion area.

公开(公告)号：US11600713B2

公开(公告)日：2023-03-07

申请号：US15993469

申请日：2018-05-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Teng Liao ,  Chia-Cheng Tai ,  Tzu-Chan Weng ,  Yi-Wei Chiu ,  Chih Hsuan Cheng

IPC: H01L29/66 ,  H01L21/3213 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/423

Abstract: A method includes forming a semiconductor fin extending a first height above a substrate, forming a dummy dielectric material over the semiconductor fin and over the substrate, forming a dummy gate material over the dummy dielectric material, the dummy gate material extending a second height above the substrate, etching the dummy gate material using multiple etching processes to form a dummy gate stack, wherein each etching process of the multiple etching processes is a different etching process, wherein the dummy gate stack has a first width at the first height, and wherein the dummy gate stack has a second width at the second height that is different from the first width.

公开(公告)号：US10170555B1

公开(公告)日：2019-01-01

申请号：US15665968

申请日：2017-08-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Teng Liao ,  Yi-Wei Chiu ,  Tzu-Chan Weng ,  Chih Hsuan Cheng

IPC: H01L21/84 ,  H01L29/08 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66

Abstract: A method includes etching a substrate to form a first semiconductor strip. A first dummy gate structure is formed over a first channel region of the first semiconductor strip. First and second recesses are etched in the first semiconductor strip on either side of a first dummy gate. An intermetallic doping film is formed in the first recess and the second recess. A dopant of the intermetallic doping film is diffused into the first semiconductor strip proximate the recesses. Source/drain regions are epitaxially grown in the recesses. A device includes semiconductor strips and a plurality of gate stacks. A first epitaxial source/drain region is interposed between a first two of the plurality of gate stacks. A first dopant diffusion area surrounds the first epitaxial source/drain region and has a first concentration of a first dopant greater than a second concentration of the first dopant outside the first dopant diffusion area.

公开(公告)号：US20180033626A1

公开(公告)日：2018-02-01

申请号：US15340636

申请日：2016-11-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Teng Liao ,  Yi-Wei Chiu ,  Chih Hsuan Cheng ,  Li-Te Hsu

IPC: H01L21/225 ,  H01L21/324 ,  H01L29/08 ,  H01L21/762 ,  H01L29/66 ,  H01L21/306 ,  H01L21/8234

CPC classification number: H01L21/2255 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/0847 ,  H01L29/66803 ,  H01L29/785

Abstract: A method includes etching a semiconductor substrate to form a first trench and a second trench. A remaining portion of the semiconductor substrate is left between the first trench and the second trench as a semiconductor region. A doped dielectric layer is formed on sidewalls of the semiconductor region and over a top surface of the semiconductor region. The doped dielectric layer includes a dopant. The first trench and the second trench are filled with a dielectric material. An anneal is then performed, and a p-type dopant or an n-type dopant in the doped dielectric layer is diffused into the semiconductor region to form a diffused semiconductor region.