公开(公告)号：US11171003B2

公开(公告)日：2021-11-09

申请号：US16204023

申请日：2018-11-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Teng Liao ,  Yi-Wei Chiu ,  Chih Hsuan Cheng ,  Li-Te Hsu

IPC分类号： H01L21/8238 ,  H01L21/225 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

摘要： A method includes etching a semiconductor substrate to form a first trench and a second trench. A remaining portion of the semiconductor substrate is left between the first trench and the second trench as a semiconductor region. A doped dielectric layer is formed on sidewalls of the semiconductor region and over a top surface of the semiconductor region. The doped dielectric layer includes a dopant. The first trench and the second trench are filled with a dielectric material. An anneal is then performed, and a p-type dopant or an n-type dopant in the doped dielectric layer is diffused into the semiconductor region to form a diffused semiconductor region.

公开(公告)号：US11043427B2

公开(公告)日：2021-06-22

申请号：US16665474

申请日：2019-10-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Ching Tsai ,  Yi-Wei Chiu ,  Li-Te Hsu

IPC分类号： H01L21/8234 ,  H01L21/762 ,  H01L29/08 ,  H01L21/02 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/3213 ,  H01L27/02 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311

摘要： A semiconductor device and method of manufacture are provided in which an the physical characteristics of a dielectric material are modified in order to provide additional benefits to surrounding structures during further processing. The modification may be performed by implanting ions into the dielectric material to form a modified region. Once the ions have been implanted, further processing relies upon the modified structure of the modified region instead of the original structure.

公开(公告)号：US11043251B2

公开(公告)日：2021-06-22

申请号：US16565640

申请日：2019-09-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Bo-Jhih Shen ,  Kuang-I Liu ,  Joung-Wei Liou ,  Jinn-Kwei Liang ,  Yi-Wei Chiu ,  Chin-Hsing Lin ,  Li-Te Hsu ,  Han-Ting Tsai ,  Cheng-Yi Wu ,  Shih-Ho Lin

IPC分类号： H01L21/00 ,  G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  G11B5/39 ,  G01R33/09

摘要： A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.

公开(公告)号：US10269624B2

公开(公告)日：2019-04-23

申请号：US15801154

申请日：2017-11-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Xi-Zong Chen ,  Y. H. Kuo ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu

IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L21/28 ,  H01L23/538 ,  H01L27/088 ,  H01L29/417 ,  H01L21/027

摘要： An embodiment method includes patterning an opening through a dielectric layer, depositing an adhesion layer along sidewalls and a bottom surface of the opening, depositing a first mask layer in the opening over the adhesion layer, etching back the first mask layer below a top surface of the dielectric layer, and widening an upper portion of the opening after etching back the first mask layer. The first mask layer masks a bottom portion of the opening while widening the upper portion of the opening. The method further includes removing the first mask layer after widening the upper portion of the opening and after removing the first mask layer, forming a contact in the opening by depositing a conductive material in the opening over the adhesion layer.

公开(公告)号：US20190006236A1

公开(公告)日：2019-01-03

申请号：US16045073

申请日：2018-07-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Tsang Hsieh ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu ,  Ying Ting Hsia

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/475 ,  H01L23/528 ,  H01L21/4757 ,  H01L29/06

摘要： A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.

公开(公告)号：US10910223B2

公开(公告)日：2021-02-02

申请号：US15340636

申请日：2016-11-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Teng Liao ,  Yi-Wei Chiu ,  Chih Hsuan Cheng ,  Li-Te Hsu

IPC分类号： H01L21/225 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

摘要： A method includes etching a semiconductor substrate to form a first trench and a second trench. A remaining portion of the semiconductor substrate is left between the first trench and the second trench as a semiconductor region. A doped dielectric layer is formed on sidewalls of the semiconductor region and over a top surface of the semiconductor region. The doped dielectric layer includes a dopant. The first trench and the second trench are filled with a dielectric material. An anneal is then performed, and a p-type dopant or an n-type dopant in the doped dielectric layer is diffused into the semiconductor region to form a diffused semiconductor region.

公开(公告)号：US10804149B2

公开(公告)日：2020-10-13

申请号：US16045073

申请日：2018-07-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Tsang Hsieh ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu ,  Ying Ting Hsia

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L23/485

摘要： A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.

公开(公告)号：US10763162B2

公开(公告)日：2020-09-01

申请号：US16423504

申请日：2019-05-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Ching Tsai ,  Yi-Wei Chiu ,  Li-Te Hsu

IPC分类号： H01L21/768

摘要： A device includes a substrate, a first dielectric layer over the substrate, a first conductive feature in the first dielectric layer, and an etch stop layer over the first dielectric layer. The etch stop layer includes metal-doped aluminum nitride. The device further includes a second dielectric layer over the etch stop layer, and a second conductive feature in the second dielectric layer. The second conductive feature extends into the etch stop layer and contacts the first conductive feature.

公开(公告)号：US10679891B2

公开(公告)日：2020-06-09

申请号：US15886190

申请日：2018-02-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Ching Tsai ,  Yi-Wei Chiu ,  Hung Jui Chang ,  Li-Te Hsu

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L23/532 ,  H01L23/522

摘要： An interconnect structure and a method of forming are provided. The method includes forming an opening in a dielectric layer and an etch stop layer, wherein the opening extends only partially through the etch stop layer. The method also includes creating a vacuum environment around the device. After creating the vacuum environment around the device, the method includes etching through the etch stop layer to extend the opening and expose a first conductive feature. The method also includes forming a second conductive feature in the opening.

公开(公告)号：US10510598B2

公开(公告)日：2019-12-17

申请号：US15386952

申请日：2016-12-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi-Tsang Hsieh ,  Cha-Hsin Chao ,  Yi-Wei Chiu ,  Li-Te Hsu ,  Ying Ting Hsia

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L23/485

摘要： A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.