公开(公告)号：US12015085B2

公开(公告)日：2024-06-18

申请号：US17874281

申请日：2022-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yan-Ting Shen ,  Chia-Chi Yu ,  Chih-Teng Liao ,  Yu-Li Lin ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A semiconductor device includes a fin structure protruding from an isolation insulating layer disposed over a substrate and having a channel region, a source/drain region disposed over the substrate, a gate dielectric layer disposed on the channel region, and a gate electrode layer disposed on the gate dielectric layer. The gate electrode includes a lower portion below a level of a top of the channel region and above an upper surface of the isolation insulating layer, and a width of the lower portion is not constant.

公开(公告)号：US11908754B2

公开(公告)日：2024-02-20

申请号：US17191905

申请日：2021-03-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jun Shimada ,  Chen-Fon Chang ,  Chih-Teng Liao

IPC: H01L21/68 ,  H01L21/66 ,  H01L21/687 ,  H01L21/67 ,  H01L21/3065

CPC classification number: H01L22/20 ,  H01L21/3065 ,  H01L21/67069 ,  H01L21/68764

Abstract: An etching apparatus is provided to be able to rotate or tilt a substrate holder on which a to-be-processed substrate is placed. According to a profile of a pre-process critical dimension of the substrate, the etching apparatus may rotate or tilt the substrate holder during an etching process in order to achieve a desired profile of a post-process critical dimension of the substrate that is related to the pre-process critical dimension.

公开(公告)号：US11621263B2

公开(公告)日：2023-04-04

申请号：US17069365

申请日：2020-10-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheng-Hung Tsai ,  Xi-Zong Chen ,  Hsiao Chien Lin ,  Chia-Tsung Tso ,  Chih-Teng Liao

IPC: H01L21/00 ,  H01L27/06 ,  H01L49/02 ,  H01L21/3213

Abstract: A method of making a semiconductor device includes steps related to forming source and drain wells of a transistor in a semiconductor substrate; forming a gate electrode of the transistor over the semiconductor substrate; forming an isolation structure in the semiconductor substrate adjacent to the transistor; and depositing a first inter-dielectric layer (ILD) material over the transistor and the isolation structure. The method also includes steps for depositing a capacitor film stack over the first ILD material, forming a pattern in the capacitor film stack over the isolation structure, and forming a capacitor plate by etching a conductive material of the capacitor film stack. Etching the conductive material includes performing a liquid etch process with a selectivity of at least 16 with regard to other materials in the capacitor film stack.

公开(公告)号：US11171003B2

公开(公告)日：2021-11-09

申请号：US16204023

申请日：2018-11-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Teng Liao ,  Yi-Wei Chiu ,  Chih Hsuan Cheng ,  Li-Te Hsu

IPC: H01L21/8238 ,  H01L21/225 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes etching a semiconductor substrate to form a first trench and a second trench. A remaining portion of the semiconductor substrate is left between the first trench and the second trench as a semiconductor region. A doped dielectric layer is formed on sidewalls of the semiconductor region and over a top surface of the semiconductor region. The doped dielectric layer includes a dopant. The first trench and the second trench are filled with a dielectric material. An anneal is then performed, and a p-type dopant or an n-type dopant in the doped dielectric layer is diffused into the semiconductor region to form a diffused semiconductor region.

公开(公告)号：US10163715B2

公开(公告)日：2018-12-25

申请号：US15789257

申请日：2017-10-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Teng Liao ,  Chih-Shan Chen ,  Yi-Wei Chiu ,  Ying Ting Hsia ,  Tzu-Chan Weng

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8238

Abstract: A FinFET device and a method of forming the same are provided. A method includes forming a fin over a substrate. An isolation region is formed adjacent the fin. A dummy gate structure is formed over the fin. The fin adjacent the dummy gate structure is recessed to form a first recess. The first recess has a U-shaped bottom surface. The U-shaped bottom surface is below a top surface of the isolation region. The first recess is reshaped to form a reshaped first recess. The reshaped first recess has a V-shaped bottom surface. At least a portion of the V-shaped bottom surface comprises one or more steps. A source/drain region is epitaxially grown in the reshaped first recess.

公开(公告)号：US20180350947A1

公开(公告)日：2018-12-06

申请号：US16045175

申请日：2018-07-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Teng Liao ,  Yi-Wei Chiu ,  Xi-Zong Chen ,  Chia-Ching Tsai

IPC: H01L29/66 ,  H01L21/321 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/28 ,  H01L23/528 ,  H01L23/485 ,  H01L21/768 ,  H01L29/423 ,  H01L29/165

CPC classification number: H01L29/66545 ,  H01L21/28123 ,  H01L21/32115 ,  H01L21/32137 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5283 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a gate spacer on a sidewall of the dummy gate stack, removing the dummy gate stack to form an opening, forming a replacement gate stack in the opening, recessing the replacement gate stack to form a recess, filling the recess with a conductive material, and performing a planarization to remove excess portions of the conductive material over the gate spacer. A remaining portion of the conductive material forms a gate contact plug. A top portion of the gate contact plug is at a same level as a top portion of the first gate spacer

公开(公告)号：US12142494B2

公开(公告)日：2024-11-12

申请号：US17341367

申请日：2021-06-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Po-Lung Hung ,  Yi-Tsang Hsieh ,  Yu-Hsi Tang ,  Chih-Teng Liao ,  Chih-Ching Cheng

IPC: H01L21/67 ,  H01J37/32

Abstract: In a method of controlling a plasma beam of a plasma etcher a flow rate controller of the plasma etcher is set to generate one or more flow rates of an etching gas corresponding to one or more plasma beams of the plasma etcher. The emitted light generated by plasma discharge corresponding to the one or more plasma beams of the plasma etcher is monitored. The flow rate controller is calibrated based on the one or more flow rates and a corresponding emitted light of the plasma discharge.

公开(公告)号：US12080582B2

公开(公告)日：2024-09-03

申请号：US17572351

申请日：2022-01-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Chi Lin ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Jen Lo ,  Chih-Teng Liao

IPC: H01L21/68 ,  H01J37/32 ,  H01L21/3065 ,  H01L21/683

CPC classification number: H01L21/6833 ,  H01J37/32082 ,  H01J37/32743 ,  H01L21/3065 ,  H01J2237/0225 ,  H01J2237/182

Abstract: A method for cleaning debris and contamination from an etching apparatus is provided. The etching apparatus includes a process chamber, a source of radio frequency power, an electrostatic chuck within the process chamber, a chuck electrode, and a source of DC power connected to the chuck electrode. The method of cleaning includes placing a substrate on a surface of the electrostatic chuck, applying a plasma to the substrate, thereby creating a positively charged surface on the surface of the substrate, applying a negative voltage or a radio frequency pulse to the electrode chuck, thereby making debris particles and/or contaminants from the surface of the electrostatic chuck negatively charged and causing them to attach to the positively charged surface of the substrate, and removing the substrate from the etching apparatus thereby removing the debris particles and/or contaminants from the etching apparatus.

公开(公告)号：US12002855B2

公开(公告)日：2024-06-04

申请号：US18075172

申请日：2022-12-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jui Fu Hsieh ,  Chih-Teng Liao ,  Chih-Shan Chen ,  Yi-Jen Chen ,  Tzu-Chan Weng

IPC: H01L29/08 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/32136 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed by a plasma etching process. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, the plasma process comprises applying pulsed bias voltage and RF voltage with pulsed power.

公开(公告)号：US10522408B2

公开(公告)日：2019-12-31

申请号：US16228924

申请日：2018-12-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Teng Liao ,  Chih-Shan Chen ,  Yi-Wei Chiu ,  Ying Ting Hsia ,  Tzu-Chan Weng

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8238

Abstract: A FinFET device and a method of forming the same are provided. A method includes forming a fin over a substrate. An isolation region is formed adjacent the fin. A dummy gate structure is formed over the fin. The fin adjacent the dummy gate structure is recessed to form a first recess. The first recess has a U-shaped bottom surface. The U-shaped bottom surface is below a top surface of the isolation region. The first recess is reshaped to form a reshaped first recess. The reshaped first recess has a V-shaped bottom surface. At least a portion of the V-shaped bottom surface comprises one or more steps. A source/drain region is epitaxially grown in the reshaped first recess.