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公开(公告)号：US20150357029A1
公开(公告)日：2015-12-10
申请号：US14830809
申请日：2015-08-20
发明人： Jung-Ping YANG , Cheng Hung LEE , Chia-En HUANG , Fu-An WU , Chih-Chieh CHIU
IPC分类号： G11C11/419
CPC分类号： G11C7/22 , G11C11/419 , G11C2207/2227
摘要： A circuit includes a supply voltage circuit, a voltage adjustment circuit, and a timing adjustment circuit. The supply voltage circuit is coupled to a memory device configured to provide a voltage level to the memory device during a write data operation. The voltage adjustment circuit is coupled to the supply voltage circuit, and is configured to provide at least one voltage level control signal to control one of a plurality of different voltages. At least one of the plurality of different voltages has a voltage level lower than a specified nominal supply voltage level. The timing adjustment circuit is coupled to the supply voltage circuit, and is configured to provide at least one voltage transition timing control signal to the supply voltage circuit. The supply voltage circuit is configured to provide at least one of the plurality of different voltages to the memory device during the write data operation.
摘要翻译： 电路包括电源电压电路，电压调节电路和定时调整电路。 电源电压电路耦合到被配置为在写入数据操作期间向存储器件提供电压电平的存储器件。 电压调节电路耦合到电源电压电路，并被配置为提供至少一个电压电平控制信号以控制多个不同电压之一。 多个不同电压中的至少一个具有低于指定的额定电源电压电平的电压电平。 定时调整电路耦合到电源电压电路，并且被配置为向电源电压电路提供至少一个电压转换定时控制信号。 电源电压电路被配置为在写入数据操作期间将多个不同电压中的至少一个提供给存储器件。
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公开(公告)号：US20190096458A1
公开(公告)日：2019-03-28
申请号：US16205534
申请日：2018-11-30
发明人： Chih-Chieh CHIU , Chia-En HUANG , Fu-An WU , I-Han HUANG , Jung-Ping YANG
IPC分类号： G11C8/10 , G11C11/419 , G11C11/418 , G11C7/02 , G11C8/14
CPC分类号： G11C8/10 , G11C7/02 , G11C8/14 , G11C11/418 , G11C11/419
摘要： An integrated circuit includes an array of write assist circuits electrically connected to a memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. Each write assist circuit is configured to receive at least a first control signal, and generate an output signal at least in response to the first control signal. The output signal controlling the operating voltage of the corresponding memory cell. Each write assist circuit includes a programmable voltage tuner. The programmable voltage tuner includes a first P-type transistor and a second P-type transistor coupled to the first P-type transistor. A first terminal of the first P-type transistor is configured as a first input node to receive a first select control signal. A first terminal of the second P-type transistor is configured as a second input node to receive a second select control signal.
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公开(公告)号：US20160019939A1
公开(公告)日：2016-01-21
申请号：US14870402
申请日：2015-09-30
CPC分类号： G11C7/12 , G11C7/106 , G11C7/1087 , G11C7/18 , G11C11/419 , G11C2207/005
摘要： A memory includes a plurality of memory blocks, a plurality of sensing circuits, a plurality of global bit lines, a common pre-charging circuit and a selection circuit. Each global bit line of the plurality of global bit lines is coupled to at least one of the memory blocks by a corresponding sensing circuit of the plurality of sensing circuits. The common pre-charging circuit is configured to individually pre-charge each global bit line of the plurality of global bit lines to a pre-charge voltage. The selection circuit is configured to selectively couple the common pre-charging circuit to a selected global bit line of the plurality of global bit lines.
摘要翻译： 存储器包括多个存储器块，多个感测电路，多个全局位线，公共预充电电路和选择电路。 多个全局位线的每个全局位线通过多个检测电路的对应检测电路耦合到至少一个存储器块。 公共预充电电路被配置为单独地将多个全局位线中的每个全局位线预充电为预充电电压。 选择电路被配置为选择性地将公共预充电电路耦合到多个全局位线的选定的全局位线。
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公开(公告)号：US20150092502A1
公开(公告)日：2015-04-02
申请号：US14039340
申请日：2013-09-27
发明人： Jung-Ping YANG , Chih-Chieh CHIU , Fu-An WU , Chia-En HUANG , I-Han HUANG
CPC分类号： G11C11/419 , G11C7/08 , G11C7/12 , G11C7/227
摘要： A circuit includes a tracking bit line, a tracking unit connected to the tracking bit line and a detection unit. The tracking unit is configured to receive a first control signal and configured to selectively charge or discharge a voltage on the tracking bit line in response to the first control signal. The detection unit is coupled to the tracking bit line and configured to generate a sense amplifier enable (SAE) signal in response to the voltage level on the tracking bit line.
摘要翻译： 电路包括跟踪位线，连接到跟踪位线的跟踪单元和检测单元。 跟踪单元被配置为接收第一控制信号并且被配置为响应于第一控制信号选择性地对跟踪位线进行充电或放电。 检测单元耦合到跟踪位线并且被配置为响应于跟踪位线上的电压电平产生读出放大器使能（SAE）信号。
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公开(公告)号：US20220343958A1
公开(公告)日：2022-10-27
申请号：US17859545
申请日：2022-07-07
发明人： Chih-Chieh CHIU , Chia-En HUANG , Fu-An WU , I-Han HUANG , Jung-Ping YANG
IPC分类号： G11C8/10 , G11C7/02 , G11C8/14 , G11C11/418 , G11C11/419
摘要： An integrated circuit includes a memory cell array, a row decoder configured to generate a first decoder signal, a column decoder configured to generate a second decoder signal, and an array of write assist circuits coupled to the row and column decoder and the memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell, and generate the output signal in response to a first control signal. The operating voltage corresponds to an output signal. Each write assist circuit includes an AND gate coupled to a programmable voltage tuner. The programmable voltage tuner includes a set of P-type transistors coupled to a first P-type transistor. The set of P-type transistors is coupled together in parallel, and receives a set of select control signals. A first terminal of the first P-type transistor is configured to receive an AND signal from the AND gate.
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公开(公告)号：US20150348616A1
公开(公告)日：2015-12-03
申请号：US14822391
申请日：2015-08-10
发明人： Chih-Chieh CHIU , Hong-Chen CHENG
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C7/08 , G11C7/227 , G11C11/4076 , G11C11/4099
摘要： A signal generating circuit includes a first circuit, a tracking circuit, and a delay circuit. The delay circuit is coupled with the first circuit and the tracking circuit. The first circuit is configured to receive a first clock signal and an output signal from an output of the delay circuit, and to generate a second clock signal and at least one first tracking signal. The tracking circuit is configured to receive the at least one first tracking signal and to generate a second tracking signal. The delay circuit is configured to receive the second clock signal and the second tracking signal and to generate the output signal.
摘要翻译： 信号发生电路包括第一电路，跟踪电路和延迟电路。 延迟电路与第一电路和跟踪电路耦合。 第一电路被配置为从延迟电路的输出接收第一时钟信号和输出信号，并且产生第二时钟信号和至少一个第一跟踪信号。 跟踪电路被配置为接收至少一个第一跟踪信号并产生第二跟踪信号。 延迟电路被配置为接收第二时钟信号和第二跟踪信号并产生输出信号。
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公开(公告)号：US20150138902A1
公开(公告)日：2015-05-21
申请号：US14086153
申请日：2013-11-21
发明人： Chih-Chieh CHIU , Chia-En HUANG , Fu-An WU , I-Han HUANG , Jung-Ping YANG
CPC分类号： G11C8/10 , G11C7/02 , G11C8/14 , G11C11/418 , G11C11/419
摘要： An integrated circuit that includes an array of memory cells and an array of write logic cells. The integrated circuit also includes a write address decoder comprising a plurality of write outputs. The array of write logic cells is electrically connected to the plurality of write outputs. The array of write logic cells is electrically connected to the array of memory cells. The array of write logic cells is configured to set an operating voltage of the memory cells.
摘要翻译： 一种集成电路，其包括存储器单元阵列和写逻辑单元阵列。 该集成电路还包括一个包含多个写输出的写地址解码器。 写入逻辑单元的阵列电连接到多个写入输出。 写入逻辑单元的阵列电连接到存储器单元阵列。 写入逻辑单元的阵列被配置为设置存储器单元的工作电压。
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公开(公告)号：US20150102853A1
公开(公告)日：2015-04-16
申请号：US14051681
申请日：2013-10-11
发明人： Jung-Ping YANG , I-Han HUANG , Chia-En HUANG , Fu-An WU , Chih-Chieh CHIU
IPC分类号： G05F1/46
CPC分类号： G05F1/46 , H03K17/163 , H03K17/164
摘要： A wake up circuit includes a bias signal control block configured to receive a sleep signal and to generate a plurality of bias control signals. The wake up circuit further includes a bias supply block configured to receive each bias control signal of the plurality of bias control signals and to generate a header bias signal. The bias supply block includes a first bias stage configured to receive a first bias control signal of the plurality of bias control signals, and to control the header bias signal to be equal to a first voltage. The bias supply block further includes a second bias stage configured to receive a second bias control signal of the plurality of bias control signals, and to control the header bias signal to be equal to a second voltage different from the first voltage. The wake up circuit further includes a header configured to receive the header bias signal, and to selectively connect a supply voltage to a load based on the header bias signal.
摘要翻译： 唤醒电路包括被配置为接收睡眠信号并产生多个偏置控制信号的偏置信号控制块。 唤醒电路还包括偏置电源模块，其被配置为接收多个偏置控制信号的每个偏置控制信号并产生报头偏置信号。 偏置电源块包括第一偏置级，其被配置为接收多个偏置控制信号的第一偏置控制信号，并且将该标题偏置信号控制为等于第一电压。 偏置电源模块进一步包括第二偏置级，其被配置为接收多个偏置控制信号的第二偏置控制信号，并且控制标题偏置信号等于与第一电压不同的第二电压。 唤醒电路还包括被配置为接收标题偏置信号的接头，并且基于报头偏置信号选择性地将电源电压连接到负载。
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公开(公告)号：US20140035664A1
公开(公告)日：2014-02-06
申请号：US13779020
申请日：2013-02-27
发明人： I-Han HUANG , Chia-En HUANG , Chih-Chieh CHIU , Fu-An WU , Chun-Jiun DAI , Hong-Chen CHENG , Jung-Ping YANG , Cheng Hung LEE
IPC分类号： G05F3/08
CPC分类号： G05F3/242 , G05F3/08 , G05F3/24 , G11C5/148 , H03K19/00361
摘要： A voltage providing circuit includes a first circuit, a second circuit coupled with the first circuit, and a third circuit coupled with the second circuit. The first circuit is configured to receive a first input signal and to generate a first output signal. The second circuit is configured to receive the first input signal and the first output signal as inputs and to generate a second output signal. The third circuit is configured to receive the second output signal and to generate an output voltage.
摘要翻译： 电压提供电路包括第一电路，与第一电路耦合的第二电路以及与第二电路耦合的第三电路。 第一电路被配置为接收第一输入信号并产生第一输出信号。 第二电路被配置为接收第一输入信号和第一输出信号作为输入并产生第二输出信号。 第三电路被配置为接收第二输出信号并产生输出电压。
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公开(公告)号：US20170125086A1
公开(公告)日：2017-05-04
申请号：US15400475
申请日：2017-01-06
发明人： Jung-Ping YANG , Chih-Chieh CHIU , Fu-An WU , Chia-En HUANG , I-Han HUANG
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C7/08 , G11C7/12 , G11C7/227
摘要： A circuit includes a tracking bit line, a first capacitive circuit, a tracking circuit and a detection circuit. The first capacitive circuit is coupled to the tracking bit line. The first capacitive circuit has a capacitive load on the tracking bit line. The tracking circuit is coupled to the tracking bit line. The tracking circuit being configured to charge or discharge a voltage on the tracking bit line based on a first control signal or the capacitive load. The detection circuit is coupled to the tracking bit line, and is configured to generate a SAE signal responsive to the voltage of the tracking bit line and an inverted first control signal.
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