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公开(公告)号：US20150357029A1
公开(公告)日：2015-12-10
申请号：US14830809
申请日：2015-08-20
发明人： Jung-Ping YANG , Cheng Hung LEE , Chia-En HUANG , Fu-An WU , Chih-Chieh CHIU
IPC分类号： G11C11/419
CPC分类号： G11C7/22 , G11C11/419 , G11C2207/2227
摘要： A circuit includes a supply voltage circuit, a voltage adjustment circuit, and a timing adjustment circuit. The supply voltage circuit is coupled to a memory device configured to provide a voltage level to the memory device during a write data operation. The voltage adjustment circuit is coupled to the supply voltage circuit, and is configured to provide at least one voltage level control signal to control one of a plurality of different voltages. At least one of the plurality of different voltages has a voltage level lower than a specified nominal supply voltage level. The timing adjustment circuit is coupled to the supply voltage circuit, and is configured to provide at least one voltage transition timing control signal to the supply voltage circuit. The supply voltage circuit is configured to provide at least one of the plurality of different voltages to the memory device during the write data operation.
摘要翻译： 电路包括电源电压电路，电压调节电路和定时调整电路。 电源电压电路耦合到被配置为在写入数据操作期间向存储器件提供电压电平的存储器件。 电压调节电路耦合到电源电压电路，并被配置为提供至少一个电压电平控制信号以控制多个不同电压之一。 多个不同电压中的至少一个具有低于指定的额定电源电压电平的电压电平。 定时调整电路耦合到电源电压电路，并且被配置为向电源电压电路提供至少一个电压转换定时控制信号。 电源电压电路被配置为在写入数据操作期间将多个不同电压中的至少一个提供给存储器件。
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公开(公告)号：US20190096458A1
公开(公告)日：2019-03-28
申请号：US16205534
申请日：2018-11-30
发明人： Chih-Chieh CHIU , Chia-En HUANG , Fu-An WU , I-Han HUANG , Jung-Ping YANG
IPC分类号： G11C8/10 , G11C11/419 , G11C11/418 , G11C7/02 , G11C8/14
CPC分类号： G11C8/10 , G11C7/02 , G11C8/14 , G11C11/418 , G11C11/419
摘要： An integrated circuit includes an array of write assist circuits electrically connected to a memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. Each write assist circuit is configured to receive at least a first control signal, and generate an output signal at least in response to the first control signal. The output signal controlling the operating voltage of the corresponding memory cell. Each write assist circuit includes a programmable voltage tuner. The programmable voltage tuner includes a first P-type transistor and a second P-type transistor coupled to the first P-type transistor. A first terminal of the first P-type transistor is configured as a first input node to receive a first select control signal. A first terminal of the second P-type transistor is configured as a second input node to receive a second select control signal.
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公开(公告)号：US20160240245A1
公开(公告)日：2016-08-18
申请号：US14920209
申请日：2015-10-22
发明人： Hao-I YANG , Chia-En HUANG , Cheng Hung LEE , Geng-Cing LIN , Jung-Ping YANG
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C7/10 , G11C7/12 , G11C7/18 , G11C7/22 , G11C8/06 , G11C8/18 , H01L27/1104 , H01L27/1116
摘要： A circuit includes a first data line, a second data line, a first pulling device, a second pulling device, a third pulling device, and a fourth pulling device. The first pulling device is configured to be activated or deactivated responsive to a first control signal; and is configured to pull a first signal at the first data line toward a voltage level of a first voltage based on a second signal at the second data line when the first pulling device is activated. The second pulling device is configured to be activated or deactivated responsive to a second control signal; and is configured to pull the second signal at the second data line toward the voltage level of the first voltage based on the first signal at the first data line when the second pulling device is activated.
摘要翻译： 电路包括第一数据线，第二数据线，第一牵引装置，第二牵引装置，第三牵引装置和第四牵引装置。 第一牵引装置被配置为响应于第一控制信号被激活或停用; 并且被配置为当第一牵引装置被激活时，基于第二数据线处的第二信号将第一数据线处的第一信号拉向第一电压的电压电平。 第二牵引装置被配置为响应于第二控制信号被激活或停用; 并且被配置为当第二拉动装置被启动时，基于第一数据线处的第一信号将第二数据线处的第二信号拉向第一电压的电压电平。
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公开(公告)号：US20160019939A1
公开(公告)日：2016-01-21
申请号：US14870402
申请日：2015-09-30
CPC分类号： G11C7/12 , G11C7/106 , G11C7/1087 , G11C7/18 , G11C11/419 , G11C2207/005
摘要： A memory includes a plurality of memory blocks, a plurality of sensing circuits, a plurality of global bit lines, a common pre-charging circuit and a selection circuit. Each global bit line of the plurality of global bit lines is coupled to at least one of the memory blocks by a corresponding sensing circuit of the plurality of sensing circuits. The common pre-charging circuit is configured to individually pre-charge each global bit line of the plurality of global bit lines to a pre-charge voltage. The selection circuit is configured to selectively couple the common pre-charging circuit to a selected global bit line of the plurality of global bit lines.
摘要翻译： 存储器包括多个存储器块，多个感测电路，多个全局位线，公共预充电电路和选择电路。 多个全局位线的每个全局位线通过多个检测电路的对应检测电路耦合到至少一个存储器块。 公共预充电电路被配置为单独地将多个全局位线中的每个全局位线预充电为预充电电压。 选择电路被配置为选择性地将公共预充电电路耦合到多个全局位线的选定的全局位线。
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公开(公告)号：US20150092502A1
公开(公告)日：2015-04-02
申请号：US14039340
申请日：2013-09-27
发明人： Jung-Ping YANG , Chih-Chieh CHIU , Fu-An WU , Chia-En HUANG , I-Han HUANG
CPC分类号： G11C11/419 , G11C7/08 , G11C7/12 , G11C7/227
摘要： A circuit includes a tracking bit line, a tracking unit connected to the tracking bit line and a detection unit. The tracking unit is configured to receive a first control signal and configured to selectively charge or discharge a voltage on the tracking bit line in response to the first control signal. The detection unit is coupled to the tracking bit line and configured to generate a sense amplifier enable (SAE) signal in response to the voltage level on the tracking bit line.
摘要翻译： 电路包括跟踪位线，连接到跟踪位线的跟踪单元和检测单元。 跟踪单元被配置为接收第一控制信号并且被配置为响应于第一控制信号选择性地对跟踪位线进行充电或放电。 检测单元耦合到跟踪位线并且被配置为响应于跟踪位线上的电压电平产生读出放大器使能（SAE）信号。
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公开(公告)号：US20220343958A1
公开(公告)日：2022-10-27
申请号：US17859545
申请日：2022-07-07
发明人： Chih-Chieh CHIU , Chia-En HUANG , Fu-An WU , I-Han HUANG , Jung-Ping YANG
IPC分类号： G11C8/10 , G11C7/02 , G11C8/14 , G11C11/418 , G11C11/419
摘要： An integrated circuit includes a memory cell array, a row decoder configured to generate a first decoder signal, a column decoder configured to generate a second decoder signal, and an array of write assist circuits coupled to the row and column decoder and the memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell, and generate the output signal in response to a first control signal. The operating voltage corresponds to an output signal. Each write assist circuit includes an AND gate coupled to a programmable voltage tuner. The programmable voltage tuner includes a set of P-type transistors coupled to a first P-type transistor. The set of P-type transistors is coupled together in parallel, and receives a set of select control signals. A first terminal of the first P-type transistor is configured to receive an AND signal from the AND gate.
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公开(公告)号：US20170018303A1
公开(公告)日：2017-01-19
申请号：US15281312
申请日：2016-09-30
发明人： Hao-I YANG , Chia-En HUANG , Cheng Hung LEE , Geng-Cing LIN , Jung-Ping YANG
IPC分类号： G11C11/419 , G11C7/18 , H01L27/11 , G11C7/12
CPC分类号： G11C11/419 , G11C7/10 , G11C7/12 , G11C7/18 , G11C7/22 , G11C8/06 , G11C8/18 , H01L27/1104 , H01L27/1116
摘要： A circuit includes: a first data line; a second data line; a write driver including first and second transistors; a first switch connected in series with the first transistor to form a first series-connected pair; a second switch in series with the second transistor to form a second series-connected pair; and a level shifter which includes the first and second transistors. The first series-connected pair is coupled between a first voltage node and the first data line. The second series-connected pair is coupled between the first voltage node and the second data line. Gate terminals of the first and second transistors are correspondingly cross-coupled with the second and first data lines.
摘要翻译： 电路包括：第一数据线; 第二条数据线 包括第一和第二晶体管的写入驱动器; 与所述第一晶体管串联连接的第一开关，以形成第一串联对; 与所述第二晶体管串联的第二开关，以形成第二串联连接对; 以及包括第一和第二晶体管的电平移位器。 第一串联对耦合在第一电压节点和第一数据线之间。 第二串联对耦合在第一电压节点和第二数据线之间。 第一和第二晶体管的栅极端子与第二和第一数据线相应地交叉耦合。
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公开(公告)号：US20160133342A1
公开(公告)日：2016-05-12
申请号：US14980250
申请日：2015-12-28
发明人： Yu-Hao HSU , Chia-En HUANG , Hektor HUANG , Yi-Ching CHANG , Chen-Lin YANG , Jung-Ping YANG , Cheng Hung LEE
IPC分类号： G11C29/00 , G11C11/417 , G11C11/419
CPC分类号： G11C29/702 , G11C11/413 , G11C11/417 , G11C11/419
摘要： An integrated circuit has a first circuit portion on a first level and a second circuit portion on a second level different from the first level. The first circuit portion includes a first cell having a first voltage value at a first node and a second voltage value at a second node. The second circuit portion includes a second cell coupled with the first cell, the second cell being selectively controllable to supply a voltage to the first cell based on an instruction to supply the voltage. The instruction to supply the voltage is based on a determined mismatch between the first voltage value and the second voltage value being greater than a predetermined threshold value.
摘要翻译： 集成电路具有第一电平上的第一电路部分和与第一电平不同的第二电平的第二电路部分。 第一电路部分包括在第一节点处具有第一电压值的第一单元和在第二节点处的第二电压值。 第二电路部分包括与第一单元耦合的第二单元，第二单元可选择地被控制，以便基于提供电压的指令向第一单元提供电压。 提供电压的指令基于第一电压值和第二电压值之间的确定的不匹配大于预定阈值。
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公开(公告)号：US20150138902A1
公开(公告)日：2015-05-21
申请号：US14086153
申请日：2013-11-21
发明人： Chih-Chieh CHIU , Chia-En HUANG , Fu-An WU , I-Han HUANG , Jung-Ping YANG
CPC分类号： G11C8/10 , G11C7/02 , G11C8/14 , G11C11/418 , G11C11/419
摘要： An integrated circuit that includes an array of memory cells and an array of write logic cells. The integrated circuit also includes a write address decoder comprising a plurality of write outputs. The array of write logic cells is electrically connected to the plurality of write outputs. The array of write logic cells is electrically connected to the array of memory cells. The array of write logic cells is configured to set an operating voltage of the memory cells.
摘要翻译： 一种集成电路，其包括存储器单元阵列和写逻辑单元阵列。 该集成电路还包括一个包含多个写输出的写地址解码器。 写入逻辑单元的阵列电连接到多个写入输出。 写入逻辑单元的阵列电连接到存储器单元阵列。 写入逻辑单元的阵列被配置为设置存储器单元的工作电压。
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公开(公告)号：US20220285375A1
公开(公告)日：2022-09-08
申请号：US17193594
申请日：2021-03-05
发明人： Geng-Cing LIN , Ze-Sian LU , Meng-Sheng CHANG , Chia-En HUANG , Jung-Ping YANG , Yen-Huei CHEN
IPC分类号： H01L27/112 , H01L23/528 , H01L21/265
摘要： An integrated circuit read only memory (ROM) structure includes a first ROM transistor with a first gate electrode, a first source, and a first drain, and a second ROM transistor with a second gate electrode, a second source, and a second drain. A drain conductive line is over the first drain and the second drain, and is between the first drain and the second drain. The first drain, the drain conductive line and the second drain are between the first gate electrode and the second gate electrode, and a first trench isolation structure electrically isolates the first drain from the first source is below the first gate electrode.
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