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    Integrated circuit design method, system and computer program product
    2.
    发明授权
    Integrated circuit design method, system and computer program product 有权

    公开(公告)号：US10997347B2

    公开(公告)日：2021-05-04

    申请号：US16577457

    申请日：2019-09-20

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： Wan-Yu Lo ,  Chung-Hsing Wang ,  Chin-Shen Lin ,  Kuo-Nan Yang

    IPC分类号： G06F30/398 ,  G06F30/392 ,  G06F111/10 ,  G06F111/20 ,  G06F119/08

    摘要： In a method, based on an operating condition of a region of an integrated circuit (IC), a first relationship between a temperature and heating power of the region is determined. Based on a cooling capacity of the region, a second relationship between the temperature and cooling power of the region is determined. Based on the first relationship and the second relationship, it is determined whether the region is thermally stable. In response to a determination that the region is thermally unstable, at least one of a structure or the operating condition of the region is changed. At least one of the determination of the first relationship, the determination of the second relationship, the determination of thermally stability of the region, or the change of at least one of the structure or the operating condition of the region is executed by a processor.

    Optimized electromigration analysis
    4.
    发明授权
    Optimized electromigration analysis 有权

    公开(公告)号：US10460070B2

    公开(公告)日：2019-10-29

    申请号：US15008546

    申请日：2016-01-28

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chin-Shen Lin ,  Ching-Shun Yang ,  Hsien Yu-Tseng

    IPC分类号： G06F17/50

    摘要： A method of determining electromigration (EM) compliance of a circuit is performed. The method includes providing a layout of the circuit, the layout comprising one or more metal lines, and changing a property of one or more of the one or more metal lines within one or more nets of a plurality of nets in the layout. Each of the nets includes a subset of the one or more metal lines. The method also includes determining one or more current values drawn only within the one or more nets and comparing the determined one or more current values drawn with corresponding threshold values. Based on the comparison, an indication is provided whether or not the layout is compliant. A pattern of the one or more metal lines in the compliant layout is transferred to a mask to be used in the manufacturing of the circuit on a substrate.

    Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement
    5.
    发明授权
    Method of fabricating semiconductor device including standard-cell-adapted power grid arrangement 有权

    公开(公告)号：US11347922B2

    公开(公告)日：2022-05-31

    申请号：US17195094

    申请日：2021-03-08

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hiranmay Biswas ,  Chung-Hsing Wang ,  Chin-Shen Lin ,  Kuo-Nan Yang

    IPC分类号： G06F30/392 ,  G06F30/3947 ,  G06F30/3953 ,  G06F30/394 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L23/00

    摘要： A method (of fabricating a power grid (PG) arrangement in a semiconductor) includes: forming a first conductive layer including segments which are conductive, including forming first segments designated for a first reference voltage and second segments designated for a second reference voltage, and interspersing the first and second segments; relative to a first direction; and forming a second conductive layer over the first conductive layer, the second conductive layer including segments that are conductive, including forming third segments designated for the first reference voltage and fourth segments designated for the second reference voltage, interspersing the third and fourth segments relative to a second direction, the second direction being perpendicular to the first direction, and arranging the segments in the second conductive layer substantially asymmetrically including, relative to the first direction, locating each fourth segment substantially asymmetrically between corresponding adjacent ones of the third segments.

    Via sizing for IR drop reduction
    6.
    发明授权
    Via sizing for IR drop reduction 有权

    公开(公告)号：US11211327B2

    公开(公告)日：2021-12-28

    申请号：US16731719

    申请日：2019-12-31

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Hiranmay Biswas ,  Chin-Shen Lin ,  Kuo-Nan Yang ,  Chung-Hsing Wang

    IPC分类号： G06F30/394 ,  H01L23/528 ,  H01L27/02 ,  H01L27/118 ,  H01L21/768 ,  H01L23/522

    摘要： A method of designing an integrated circuit device includes receiving an initial design of an integrated circuit, including a selection and location of a functional group of integrated circuit components, a power grid with multiple layers of conductive lines for supplying power to the components, and vias of one or more initial sizes interconnecting the conductive lines of different layers. The method further includes determining, based on a predetermined criterion such as the existence of unoccupied space for a functional unit, that a via modification can be made. The method further includes substituting the one or more of the via with a modified via of a larger cross-sectional area or a plurality of vias having a larger total cross-sectional area than the initial via. The method further includes confirming that the modified design complies with a predetermined set of design rules.