公开(公告)号：US12100436B2

公开(公告)日：2024-09-24

申请号：US18321552

申请日：2023-05-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hidehiro Fujiwara ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Wei-Chang Zhao

IPC: G11C16/04 ,  G11C11/412 ,  G11C11/419 ,  H01L27/02 ,  H10B10/00

CPC classification number: G11C11/419 ,  G11C11/412 ,  H01L27/0207 ,  H10B10/12

Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.

公开(公告)号：US11322198B2

公开(公告)日：2022-05-03

申请号：US17120640

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hidehiro Fujiwara ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Wei-Chang Zhao

IPC: G11C11/418

Abstract: A memory macro system may be provided. The memory macro system may comprise a first segment, a second segment, a first WL, and a second WL. The first segment may comprise a first plurality of memory cells. The second segment may comprise a second plurality of memory cells. The first segment may be positioned over the second segment. The first WL may correspond to the first segment and the second WL may correspond to the second segment. The first WL and the second WL may be configured to be activated in one cycle.

公开(公告)号：US20210343317A1

公开(公告)日：2021-11-04

申请号：US17372540

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hidehiro Fujiwara ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Wei-Chang Zhao

IPC: G11C5/06 ,  H01L27/11 ,  H01L27/092

Abstract: A semiconductor chip is provided. The semiconductor chip includes a SRAM cell, a logic cell, a signal line and a ground line. The SRAM cell includes a storage transmission gate, a read transmission gate and a latch circuit. The latch circuit is serially connected between the storage and read transmission gates, and includes a first inverter, a second inverter and a transmission gate connected to an output of the first inverter, an input of the second inverter and an output of the storage transmission gate. The logic cell disposed aside the SRAM cell is connected with the SRAM cell by first and second active structures. The signal and ground lines extend at opposite sides of the SRAM and logic cells, and are substantially parallel with the first and second active structures. The SRAM and logic cells are disposed between and electrically connected to the signal and ground lines.

公开(公告)号：US11018142B2

公开(公告)日：2021-05-25

申请号：US16457553

申请日：2019-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Yasutoshi Okuno

IPC: H01L27/11 ,  H01L23/528 ,  H01L23/522 ,  H01L27/02 ,  G06F30/392

Abstract: A memory cell includes a first and second pull up transistor, a first and second pass gate transistor and a metal contact. The first pull up transistor has a first active region extending in a first direction. The first pass gate transistor has a second active region extending in the first direction, and being separated from the first active region in a second direction. The second active region is adjacent to the first active region. The second pass gate transistor is coupled to the second pull up transistor. The metal contact extends in the second direction, and extends from the first active region to the second active region. The metal contact couples drains of the first pull up transistor and the first pass gate transistor. The first and second pass gate transistors and the first and second pull up transistors are part of a four transistor memory cell.

公开(公告)号：US10892008B2

公开(公告)日：2021-01-12

申请号：US16434746

申请日：2019-06-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hidehiro Fujiwara ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Wei-Chang Zhao

IPC: G11C11/418

Abstract: A memory macro system may be provided. The memory macro system may comprise a first segment, a second segment, a first WL, and a second WL. The first segment may comprise a first plurality of memory cells. The second segment may comprise a second plurality of memory cells. The first segment may be positioned over the second segment. The first WL may correspond to the first segment and the second WL may correspond to the second segment. The first WL and the second WL may be configured to be activated in one cycle.

公开(公告)号：US11657870B2

公开(公告)日：2023-05-23

申请号：US17381234

申请日：2021-07-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hidehiro Fujiwara ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Wei-Chang Zhao

IPC: G11C16/04 ,  G11C11/419 ,  H01L27/02 ,  H01L27/11 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/1104

Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.

公开(公告)号：US11637108B2

公开(公告)日：2023-04-25

申请号：US17325641

申请日：2021-05-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hidehiro Fujiwara ,  Chih-Yu Lin ,  Hsien-Yu Pan ,  Yasutoshi Okuno ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: H01L27/11 ,  H01L23/528 ,  H01L27/02 ,  H01L23/522 ,  G06F30/392

Abstract: A method of forming a memory circuit includes generating a layout design of the memory circuit, and manufacturing the memory circuit based on the layout design. The memory circuit is a four transistor memory cell that includes at least the first pass gate transistor and the first pull up transistor. The generating of the layout design includes generating a first active region layout pattern corresponding to fabricating a first active region of a first pull up transistor, generating a second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, and generating a first metal contact layout pattern corresponding to fabricating a first metal contact is electrically coupled to a source of the first pull up transistor. The first metal contact layout pattern extends in a second direction, overlaps a cell boundary of the memory circuit and the first active region layout pattern.

公开(公告)号：US11074966B2

公开(公告)日：2021-07-27

申请号：US16659055

申请日：2019-10-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hidehiro Fujiwara ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Wei-Chang Zhao

IPC: G11C8/00 ,  G11C11/419 ,  H01L27/02 ,  H01L27/11 ,  G11C11/412

Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.

公开(公告)号：US10964683B2

公开(公告)日：2021-03-30

申请号：US15904959

申请日：2018-02-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hidehiro Fujiwara ,  Hung-Jen Liao ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Sahil Preet Singh

IPC: H01L27/02 ,  H01L27/11 ,  H01L23/522 ,  G11C5/06 ,  G11C7/18

Abstract: A memory array includes a column of cells arranged along a first direction and a bit line extending along the first direction over the column of cells. The column of cells includes a set of memory cells and a set of strap cells. The bit line includes a first conductor in a second conductor. The first conductor extends in the first direction and is in a first conductive layer. The second conductor extends in the first direction and is in a second conductive layer different from the first conductive layer.

公开(公告)号：US20250054537A1

公开(公告)日：2025-02-13

申请号：US18788879

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hidehiro Fujiwara ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Wei-Chang Zhao

IPC: G11C11/419 ,  G11C11/412 ,  H01L27/02 ,  H10B10/00

Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.