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51 条记录 (耗时 0.028 秒)

    Memory array circuit and method of manufacturing same
    2.
    发明授权
    Memory array circuit and method of manufacturing same 有权

    公开(公告)号：US11637108B2

    公开(公告)日：2023-04-25

    申请号：US17325641

    申请日：2021-05-20

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hidehiro Fujiwara ,  Chih-Yu Lin ,  Hsien-Yu Pan ,  Yasutoshi Okuno ,  Yen-Huei Chen ,  Hung-Jen Liao

    IPC分类号： H01L27/11 ,  H01L23/528 ,  H01L27/02 ,  H01L23/522 ,  G06F30/392

    摘要： A method of forming a memory circuit includes generating a layout design of the memory circuit, and manufacturing the memory circuit based on the layout design. The memory circuit is a four transistor memory cell that includes at least the first pass gate transistor and the first pull up transistor. The generating of the layout design includes generating a first active region layout pattern corresponding to fabricating a first active region of a first pull up transistor, generating a second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, and generating a first metal contact layout pattern corresponding to fabricating a first metal contact is electrically coupled to a source of the first pull up transistor. The first metal contact layout pattern extends in a second direction, overlaps a cell boundary of the memory circuit and the first active region layout pattern.

    Four CPP wide memory cell with buried power grid, and method of fabricating same
    3.
    发明授权
    Four CPP wide memory cell with buried power grid, and method of fabricating same 有权

    公开(公告)号：US11569246B2

    公开(公告)日：2023-01-31

    申请号：US17225627

    申请日：2021-04-08

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Hidehiro Fujiwara ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Wei-Chang Zhao ,  Yi-Hsin Nien

    IPC分类号： H01L27/11 ,  G06F30/392 ,  H01L23/522 ,  H01L23/528 ,  G03F1/70

    摘要： A memory device including: active regions; gate electrodes which are substantially aligned relative to four corresponding track lines such that the memory device has a width of four contacted poly pitch (4 CPP) and are electrically coupled to the active regions; contact-to-transistor-component structures (MD structures) which are electrically coupled to the active regions, and are interspersed among corresponding ones of the gate electrodes; via-to-gate/MD (VGD) structures which are electrically coupled to the gate electrodes and the MD structures; conductive segments which are in a first layer of metallization (M_1st layer), and are electrically coupled to the VGD structures; buried contact-to-transistor-component structures (BVD structures) which are electrically coupled to the active regions; and buried conductive segments which are in a first buried layer of metallization (BM_1st layer), and are electrically coupled to the BVD structures, and correspondingly provide a first reference voltage or a second reference voltage.

    Memory device having a negative voltage circuit
    4.
    发明授权
    Memory device having a negative voltage circuit 有权

    公开(公告)号：US11562786B2

    公开(公告)日：2023-01-24

    申请号：US17082404

    申请日：2020-10-28

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yi-Hsin Nien ,  Hidehiro Fujiwara ,  Chih-Yu Lin ,  Yen-Huei Chen

    IPC分类号： G11C11/419

    摘要： A memory device is provided. The memory device includes a memory cell and a bit line connected to the memory cell. A negative voltage generator is connected to the bit line. The negative voltage generator, when enabled, is operative to provide a first write path for the bit line. A control circuit is connected to the negative voltage generator and the bit line. The control circuit is operative to provide a second write path for the bit line when the negative voltage generator is not enabled.

    Method and system to balance ground bounce
    6.
    发明授权
    Method and system to balance ground bounce 有权

    公开(公告)号：US11074966B2

    公开(公告)日：2021-07-27

    申请号：US16659055

    申请日：2019-10-21

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Hidehiro Fujiwara ,  Hsien-Yu Pan ,  Chih-Yu Lin ,  Yen-Huei Chen ,  Wei-Chang Zhao

    IPC分类号： G11C8/00 ,  G11C11/419 ,  H01L27/02 ,  H01L27/11 ,  G11C11/412

    摘要： A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.

    Memory device
    9.
    发明授权
    Memory device 有权
    内存设备

    公开(公告)号：US09449661B2

    公开(公告)日：2016-09-20

    申请号：US14799780

    申请日：2015-07-15

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Yen-Huei Chen ,  Li-Wen Wang ,  Chih-Yu Lin

    IPC分类号： G11C7/22 ,  G11C7/12 ,  G11C11/419

    CPC分类号： G11C7/22 ,  G11C7/12 ,  G11C11/419

    摘要： A memory device includes a memory cell electrically connected to a power line and a power supply unit configured to control a voltage level on the power line. The power supply unit receives a control signal corresponding to a write cycle of the memory cell and, responsive to a first state of the control signal, outputs a first voltage level on the power line. Responsive to a second state of the control signal, the power supply unit outputs a second voltage level on the power line, the second voltage level having a magnitude less than a magnitude of the first voltage level.

    摘要翻译： 存储装置包括电连接到电力线的存储单元和被配置为控制电力线上的电压电平的电源单元。 电源单元接收对应于存储单元的写入周期的控制信号，并且响应于控制信号的第一状态在电力线上输出第一电压电平。 响应于控制信号的第二状态，电源单元在电力线上输出第二电压电平，第二电压电平具有小于第一电压电平的幅度的幅度。

    Memory device with tracking mechanism
    10.
    发明授权
    Memory device with tracking mechanism 有权
    具有跟踪机制的存储设备

    公开(公告)号：US09389786B2

    公开(公告)日：2016-07-12

    申请号：US14300750

    申请日：2014-06-10

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Ming-Chien Tsai ,  Yu-Hao Hsu ,  Chih-Yu Lin ,  Chen-Lin Yang ,  Cheng Hung Lee

    IPC分类号： H03M13/00 ,  G06F3/06

    CPC分类号： G06F3/0604 ,  G06F3/0653 ,  G06F3/0679 ,  G06F12/00 ,  G11C5/025 ,  G11C7/06 ,  G11C7/08 ,  G11C7/227 ,  G11C11/419

    摘要： A memory device includes storage layers each comprising memory cells arranged in a plurality of rows, bit lines coupled to the memory cells in the corresponding rows, tracking cells arranged in at least one row, at least one tracking bit line coupled to the tracking cells, and at least one sense amplifier coupled to the bit lines. The sense amplifier is configured to detect data stored in the memory cells, and has an enabling terminal coupled to the at least one tracking bit line. The memory device further comprises word lines and tracking word lines extending through the storage layers. The word lines are coupled to the corresponding memory cells in the storage layers. The tracking word lines are coupled to the corresponding tracking cells in the storage layers.

    摘要翻译： 存储器件包括存储层，每个存储层包括布置在多行中的存储单元，耦合到相应行中的存储器单元的位线，布置在至少一行中的跟踪单元，耦合到跟踪单元的至少一个跟踪位线， 以及耦合到位线的至少一个读出放大器。 读出放大器被配置为检测存储在存储器单元中的数据，并且具有耦合到至少一个跟踪位线的使能端。 存储器件还包括延伸穿过存储层的字线和跟踪字线。 字线耦合到存储层中的相应存储单元。 跟踪字线被耦合到存储层中的对应的跟踪单元。