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公开(公告)号：US12119052B2
公开(公告)日：2024-10-15
申请号：US18362736
申请日：2023-07-31
IPC分类号： G11C11/419 , G11C11/418
CPC分类号： G11C11/419 , G11C11/418
摘要： A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
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公开(公告)号：US12100436B2
公开(公告)日：2024-09-24
申请号：US18321552
申请日：2023-05-22
发明人： Hidehiro Fujiwara , Hsien-Yu Pan , Chih-Yu Lin , Yen-Huei Chen , Wei-Chang Zhao
IPC分类号： G11C16/04 , G11C11/412 , G11C11/419 , H01L27/02 , H10B10/00
CPC分类号： G11C11/419 , G11C11/412 , H01L27/0207 , H10B10/12
摘要： A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.
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公开(公告)号：US20240212747A1
公开(公告)日：2024-06-27
申请号：US18601512
申请日：2024-03-11
发明人： Hidehiro Fujiwara , Kao-Cheng Lin , Wei Min Chan , Yen-Huei Chen
IPC分类号： G11C11/418 , G11C11/412 , G11C11/419 , H03K17/687
CPC分类号： G11C11/418 , G11C11/412 , H03K17/6871 , G11C11/419
摘要： A device includes a first power rail for a first power domain and a second power rail for a second power domain. A first circuit block is connected to the first power rail and a second circuit block is connected to the second power rail. The first and second circuit blocks are both connected to a virtual VSS terminal. A footer circuit is connected between the virtual VSS terminal and a ground terminal, and the footer circuit is configured to selectively control a connection between the virtual VSS terminal and the ground terminal.
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公开(公告)号：US20240145385A1
公开(公告)日：2024-05-02
申请号：US18170443
申请日：2023-02-16
发明人： Yi-Hsin Nien , Hidehiro Fujiwara , Chih-Yu Lin , Yen-Huei Chen
IPC分类号： H01L23/528 , H01L25/18 , H10B10/00 , H10B80/00
CPC分类号： H01L23/5283 , H01L25/18 , H10B10/125 , H10B80/00
摘要： A memory device includes a plurality of memory cells disposed over a substrate and formed as an array that has a plurality of rows and a plurality of columns. Each of the plurality of memory cells includes a plurality of transistors. A first subset of the plurality of memory cells, that are disposed in first neighboring ones of the plurality of rows, are physically coupled to a corresponding one of a plurality of second interconnect structures that carries a supply voltage through a corresponding one of a plurality of first interconnect structures. The plurality of first interconnect structures extend along a first lateral direction in parallel with a lengthwise direction of a channel of each of the transistors of the memory cells, and the plurality of second interconnect structures, disposed above the plurality of first interconnect structures, extend along a second lateral direction perpendicular to the first lateral direction.
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公开(公告)号：US20240105241A1
公开(公告)日：2024-03-28
申请号：US18170426
申请日：2023-02-16
发明人： Chih-Yu Lin , Yi-Hsin Nien , Hidehiro Fujiwara , Yen-Huei Chen
摘要： Disclosed herein are related to a memory device. In one aspect, a memory device includes a set of memory cells. In one aspect, the memory device includes a first bit line extending along a direction. The first bit line may be coupled to a subset of the set of memory cells disposed along the direction. In one aspect, the memory device includes a second bit line extending along the direction. In one aspect, the memory device includes a switch coupled between the first bit line and the second bit line.
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公开(公告)号：US11763882B2
公开(公告)日：2023-09-19
申请号：US17814700
申请日：2022-07-25
IPC分类号： G11C11/419 , G11C11/418
CPC分类号： G11C11/419 , G11C11/418
摘要： A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
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公开(公告)号：US11723194B2
公开(公告)日：2023-08-08
申请号：US17193594
申请日：2021-03-05
发明人： Geng-Cing Lin , Ze-Sian Lu , Meng-Sheng Chang , Chia-En Huang , Jung-Ping Yang , Yen-Huei Chen
IPC分类号： H01L27/112 , H10B20/00 , H01L21/265 , H01L23/528
CPC分类号： H10B20/34 , H01L21/26513 , H01L23/5286
摘要： An integrated circuit read only memory (ROM) structure includes a first ROM transistor with a first gate electrode, a first source, and a first drain, and a second ROM transistor with a second gate electrode, a second source, and a second drain. A drain conductive line is over the first drain and the second drain, and is between the first drain and the second drain. The first drain, the drain conductive line and the second drain are between the first gate electrode and the second gate electrode, and a first trench isolation structure electrically isolates the first drain from the first source is below the first gate electrode.
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公开(公告)号：US11562946B2
公开(公告)日：2023-01-24
申请号：US17209878
申请日：2021-03-23
发明人： Hidehiro Fujiwara , Tze-Chiang Huang , Hong-Chen Cheng , Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yun-Han Lee , Lee-Chung Lu
IPC分类号： G11C11/00 , H01L23/48 , G11C11/418 , H01L21/768 , H01L27/11
摘要： A memory macro structure includes a first memory array, a second memory array, a cell activation circuit coupled to the first and second memory arrays and positioned between the first and second memory arrays, a control circuit coupled to the cell activation circuit and positioned adjacent to the cell activation circuit, and a through-silicon via (TSV) extending through one of the cell activation circuit or the control circuit.
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公开(公告)号：US20220139450A1
公开(公告)日：2022-05-05
申请号：US17084635
申请日：2020-10-30
发明人： Hidehiro Fujiwara , Hung-Jen Liao , Yen-Huei Chen
IPC分类号： G11C11/419
摘要： The disclosure introduces a write assist scheme that boost the word line of a selected memory cell by using a parasitic capacitor element coupled between the word line and a bit line of at least one unselected memory cell. The SRAM includes a word line, a first bit line, a second bit line, a first memory cell coupled to the first bit line and the word line, a second memory cell coupled to the second bit line and the word line, and a write assist circuit coupled to the second bit line. The write assist circuit is configured to clamp the second bit line to the word line during a write operation of the first memory cell.
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公开(公告)号：US11322198B2
公开(公告)日：2022-05-03
申请号：US17120640
申请日：2020-12-14
发明人： Hidehiro Fujiwara , Hsien-Yu Pan , Chih-Yu Lin , Yen-Huei Chen , Wei-Chang Zhao
IPC分类号： G11C11/418
摘要： A memory macro system may be provided. The memory macro system may comprise a first segment, a second segment, a first WL, and a second WL. The first segment may comprise a first plurality of memory cells. The second segment may comprise a second plurality of memory cells. The first segment may be positioned over the second segment. The first WL may correspond to the first segment and the second WL may correspond to the second segment. The first WL and the second WL may be configured to be activated in one cycle.
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