利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

44 条记录 (耗时 0.032 秒)

    Interconnect Structures and Methods of Forming the Same
    5.
    发明申请
    Interconnect Structures and Methods of Forming the Same 审中-公开

    公开(公告)号：US20200006224A1

    公开(公告)日：2020-01-02

    申请号：US16569912

    申请日：2019-09-13

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Sung-Li Wang ,  Yasutoshi Okuno

    IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L21/768

    摘要： Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.

    FinFET with metal gate stressor
    8.
    发明授权
    FinFET with metal gate stressor 有权
    FinFET与金属栅应力

    公开(公告)号：US09054213B2

    公开(公告)日：2015-06-09

    申请号：US14502925

    申请日：2014-09-30

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Andrew Joseph Kelly ,  Yasutoshi Okuno ,  Pei-Shan Chien ,  Wei-Hsiung Tseng

    IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L21/285

    CPC分类号： H01L29/7851 ,  H01L21/28556 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/7845 ,  H01L29/785

    摘要： A gate stressor for a fin field effect transistor (FinFET) device is provided. The gate stressor includes a floor, a first stressor sidewall, and a second stressor sidewall. The floor is formed on a first portion of a gate layer. The gate layer is disposed above a shallow trench isolation (STI) region. The first stressor sidewall formed on a second portion of the gate layer. The second portion of the gate layer is disposed on sidewalls of a fin. The second stressor sidewall formed on the third portion of the gate layer. The third portion of the gate layer is disposed on sidewalls of a structure spaced apart from the fin. The first stressor side wall and the second stressor sidewall do not exceed a height of the fin.

    摘要翻译： 提供了一种用于鳍式场效应晶体管（FinFET）器件的栅极应力器。 闸应力器包括地板，第一应力侧壁和第二应力侧壁。 地板形成在栅极层的第一部分上。 栅极层设置在浅沟槽隔离（STI）区域的上方。 第一应力侧壁形成在栅极层的第二部分上。 栅极层的第二部分设置在翅片的侧壁上。 第二应力侧壁形成在栅极层的第三部分上。 栅极层的第三部分设置在与散热片间隔开的结构的侧壁上。 第一应力侧壁和第二应力侧壁不超过翅片的高度。

    Stress Analysis of 3-D Structures Using Tip-Enhanced Raman Scattering Technology
    9.
    发明申请
    Stress Analysis of 3-D Structures Using Tip-Enhanced Raman Scattering Technology 有权
    使用尖端增强拉曼散射技术的三维结构的应力分析

    公开(公告)号：US20150062561A1

    公开(公告)日：2015-03-05

    申请号：US14017079

    申请日：2013-09-03

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Liang-Gi Yao ,  Yasutoshi Okuno ,  Wei-Shan Hu ,  Yusuke Oniki ,  Ling-Yen Yeh ,  Clement Hsingjen Wann

    IPC分类号： G01N21/65 ,  G01Q30/02

    CPC分类号： G01N21/65 ,  G01N21/658 ,  G01Q30/02

    摘要： A method includes performing a first probing on a sample integrated circuit structure to generate a first Raman spectrum. During the first probing, a first laser beam having a first wavelength is projected on the sample integrated circuit structure. The method further includes performing a second probing on the sample integrated circuit structure to generate a second Raman spectrum, wherein a Tip-Enhanced Raman Scattering (TERS) method is used to probe the sample integrated circuit structure. During the second probing, a second laser beam having a second wavelength different from the first wavelength is projected on the sample integrated circuit structure. A stress in a first probed region of the sample integrated circuit structure is then from the first Raman spectrum and the second Raman spectrum.

    摘要翻译： 一种方法包括对采样集成电路结构执行第一探测以产生第一拉曼光谱。 在第一次探测期间，具有第一波长的第一激光束投射在样品集成电路结构上。 该方法还包括在样本集成电路结构上执行第二探测以产生第二拉曼光谱，其中使用尖端增强拉曼散射（TERS）方法来探测样本集成电路结构。 在第二次探测期间，具有与第一波长不同的第二波长的第二激光束投射在样本集成电路结构上。 然后，样品集成电路结构的第一探测区域中的应力来自第一拉曼光谱和第二拉曼光谱。