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1.发明公开公开(公告)号：US20230197633A1
公开(公告)日：2023-06-22
申请号：US18173080
申请日：2023-02-23
Inventor： Nuo Xu , Yuan-Hao Chang , Po-Sheng Lu , Zhiqiang Wu
IPC: H01L23/552 , H01L23/00 , H01L25/065
CPC classification number: H01L23/552 , H01L24/13 , H01L25/0657 , H01L2224/13005 , H01L2225/06541 , H01L2225/06565 , H01L2225/06586 , H01L2924/1435
Abstract: A semiconductor package, a semiconductor device and a shielding housing for a semiconductor package are provided. The semiconductor package includes a semiconductor chip having a first region and a second region beside the first region; and a shielding housing encasing the semiconductor chip, made of a magnetic permeable material, and including a first shielding plate, a second shielding plate opposite to the first shielding plate and a shielding wall extending between the first shielding plate and the second shielding plate. The first shielding plate has an opening exposing the first region and includes a raised portion surrounding the opening and a flat portion beside the raised portion and shielding the second region. A first distance from a level of the semiconductor chip to an outer surface of the raised portion is greater than a second distance from the level to an outer surface of the flat portion.
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公开(公告)号：US20240112842A1
公开(公告)日：2024-04-04
申请号：US18152726
申请日：2023-01-10
Inventor： Po-Sheng Lu , Chien-Hung Liu , Nuo Xu
IPC: H01F17/02
CPC classification number: H01F17/02 , H01L28/10 , H01F2017/0086
Abstract: An inductor and a method of forming the same are provided. The inductor includes a patterned wire structure. The patterned wire structure includes a conductive core, a dielectric film and a magnetic shell. The conductive core includes a pair of end surfaces and an outer surface between the pair of end surfaces. The dielectric film covers the outer surface. The magnetic shell covers the dielectric film. The dielectric film is between the conductive core and the magnetic shell.
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公开(公告)号：US20230389447A1
公开(公告)日：2023-11-30
申请号：US18446563
申请日：2023-08-09
Inventor： Tsung-Chieh Hsiao , Po-Sheng Lu , Wei-Chih Wen , Liang-Wei Wang , Yu-Jen Wang , Dian-Hau Chen , Yen-Ming Chen
Abstract: A method of forming a semiconductor device includes providing a bottom electrode; a magnetic tunneling junction (MTJ) element over the bottom electrode; a top electrode over the MTJ element; and a sidewall spacer abutting the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacer includes a magnetic material.
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4.发明授权公开(公告)号：US11610848B2
公开(公告)日：2023-03-21
申请号：US17340089
申请日：2021-06-07
Inventor： Nuo Xu , Yuan-Hao Chang , Po-Sheng Lu , Zhiqiang Wu
IPC: H01L23/552 , H01L23/00 , H01L25/065
Abstract: A semiconductor package, a semiconductor device and a shielding housing for a semiconductor package are provided. The semiconductor package includes a semiconductor chip having a first region and a second region beside the first region; and a shielding housing encasing the semiconductor chip, made of a magnetic permeable material, and including a first shielding plate, a second shielding plate opposite to the first shielding plate and a shielding wall extending between the first shielding plate and the second shielding plate. The first shielding plate has an opening exposing the first region and includes a raised portion surrounding the opening and a flat portion beside the raised portion and shielding the second region. A first distance from a level of the semiconductor chip to an outer surface of the raised portion is greater than a second distance from the level to an outer surface of the flat portion.
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公开(公告)号：US20240389466A1
公开(公告)日：2024-11-21
申请号：US18788450
申请日：2024-07-30
Inventor： Chih-Fan Huang , Po-Sheng Lu , Chen-Chiu Huang , Dian-Hau Chen , Yen-Ming Chen
Abstract: A semiconductor device includes a bottom electrode and a magnetic tunneling junction (MTJ) element over the bottom electrode. The MTJ element includes a top magnetic plate, a bottom magnetic plate, and a barrier layer between the top magnetic plate and the bottom magnetic plate. An edge portion of the bottom magnetic plate extends beyond sidewalls of the top magnetic plate. The semiconductor device also includes a spacer disposed on the sidewalls of the top magnetic plate but not on sidewalls of the bottom magnetic plate, and a top electrode over the top magnetic plate.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20240371786A1
公开(公告)日：2024-11-07
申请号：US18772227
申请日：2024-07-14
Inventor： Nuo Xu , Yuan-Hao Chang , Po-Sheng Lu , Zhiqiang Wu
IPC: H01L23/552 , H01L23/00 , H01L25/065
Abstract: A semiconductor package, a semiconductor device and a shielding housing for a semiconductor package are provided. The semiconductor package includes a semiconductor chip having a first region and a second region beside the first region; and a shielding housing encasing the semiconductor chip, made of a magnetic permeable material, and including a first shielding plate, a second shielding plate opposite to the first shielding plate and a shielding wall extending between the first shielding plate and the second shielding plate. The first shielding plate has an opening exposing the first region and includes a raised portion surrounding the opening and a flat portion beside the raised portion and shielding the second region. A first distance from a level of the semiconductor chip to an outer surface of the raised portion is greater than a second distance from the level to an outer surface of the flat portion.
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公开(公告)号：US12004431B2
公开(公告)日：2024-06-04
申请号：US17206527
申请日：2021-03-19
Inventor： Tsung-Chieh Hsiao , Po-Sheng Lu , Wei-Chih Wen , Liang-Wei Wang , Yu-Jen Wang , Dian-Hau Chen , Yen-Ming Chen
Abstract: A semiconductor device includes a bottom electrode; a magnetic tunneling junction (MTJ) element over the bottom electrode; a top electrode over the MTJ element; and a sidewall spacer abutting the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacer includes a magnetic material.
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公开(公告)号：US20240016066A1
公开(公告)日：2024-01-11
申请号：US17861234
申请日：2022-07-10
Inventor： Po-Sheng Lu , Zhi-Ren Xiao , Nuo Xu , Zhiqiang Wu
CPC classification number: H01L43/04 , H01L27/228 , H01L43/06 , H01L43/14
Abstract: A memory device includes a substrate, a reference layer, a tunneling layer, a film stack, and a capping layer. The reference layer is disposed on the substrate. The tunneling layer is disposed on the reference layer. The film stack is formed over the tunneling layer and on the substrate, wherein the film stack includes a first free layer, a spacer with high exchange stiffness constant and a second free layer. The first free layer is in contact with the tunneling layer and the film stack. The spacer with high exchange stiffness constant is sandwiched between the first free layer and the second free layer. The capping layer is disposed on and electrically connected to the film stack.
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9.发明申请公开(公告)号：US20220392847A1
公开(公告)日：2022-12-08
申请号：US17340089
申请日：2021-06-07
Inventor： Nuo Xu , Yuan-Hao Chang , Po-Sheng Lu , Zhiqiang Wu
IPC: H01L23/552 , H01L23/00 , H01L25/065
Abstract: A semiconductor package, a semiconductor device and a shielding housing for a semiconductor package are provided. The semiconductor package includes a semiconductor chip having a first region and a second region beside the first region; and a shielding housing encasing the semiconductor chip, made of a magnetic permeable material, and including a first shielding plate, a second shielding plate opposite to the first shielding plate and a shielding wall extending between the first shielding plate and the second shielding plate. The first shielding plate has an opening exposing the first region and includes a raised portion surrounding the opening and a flat portion beside the raised portion and shielding the second region. A first distance from a level of the semiconductor chip to an outer surface of the raised portion is greater than a second distance from the level to an outer surface of the flat portion.
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公开(公告)号：US20240381783A1
公开(公告)日：2024-11-14
申请号：US18778989
申请日：2024-07-21
Inventor： Nuo Xu , Yuan Hao Chang , Po-Sheng Lu , Zhiqiang Wu
Abstract: An MRAM cell block and a magnetic shielding structure for the MRAM cell block are incorporated into a metal interconnect of an integrated circuit (IC) device. The magnetic shielding structure may be provided by metallization layers and via layers having wires and vias that incorporate a magnetic shielding material. The magnetic shielding material may form the wires and vias, form a liner around the wires, or may be a layer of the wires. The wires and vias may also include a metal that is more conductive than the magnetic shielding material. The metal interconnect may include layers above or below the magnetic shielding structure that lack the magnetic shielding material and are more conductive. The MRAM cell block with the magnetic shielding structure is optionally provided as a standalone memory device or incorporated into a 3-D IC device that includes a second substrate having a conventional metal interconnect.
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