公开(公告)号：US11417588B2

公开(公告)日：2022-08-16

申请号：US16943806

申请日：2020-07-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Wei-Ren Chen ,  Chih-Liang Chen ,  Wei-Ling Chang ,  Hui-Zhong Zhuang ,  Li-Chun Tien

IPC分类号： H01L23/48 ,  H01L21/48 ,  H01L27/02

摘要： A semiconductor structure includes a plurality of vias and a metal layer. The vias disposed on a semiconductor substrate. The metal layer has a plurality of metal lines and at least one transmission gate line region. The metal lines are connected to the vias. The at least one transmission gate line region is connected to at least one transmission gate corresponding to at least one transmission gate circuit. The transmission gate line region includes at least one different-net via pair. The different-net via pair has two metal lines and each of the two metal lines is connected to a via respectively. The two metal lines extend along a first axis but toward opposite directions. A distance between the two vias of the different-net via pair is within about 1.5 poly pitch.

公开(公告)号：US20230369320A1

公开(公告)日：2023-11-16

申请号：US18182657

申请日：2023-03-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ya-Chi Chou ,  Wei-Ling Chang ,  Wei-Ren Chen ,  Chi-Yu Lu

IPC分类号： H01L27/088 ,  H01L27/092 ,  H01L21/762

CPC分类号： H01L27/088 ,  H01L27/092 ,  H01L21/76224

摘要： A device includes a substrate, a first well region, a second well region, and a dummy region in the substrate, where the dummy region is a non-functional region situated between the first well region and the second well region. The first well region is configured to receive a first voltage and the second well region is configured to receive a second voltage that is different than the first voltage. The device further includes an active region that extends through at least part of the first well region and at least part of the dummy region, and at least one isolation structure situated in the dummy region between a first gate structure that extends over the active region in the dummy region on one side of the at least one isolation structure and a second gate structure on another side of the at least one isolation structure.

公开(公告)号：US11715733B2

公开(公告)日：2023-08-01

申请号：US17313474

申请日：2021-05-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Ren Chen ,  Cheng-Yu Lin ,  Hui-Zhong Zhuang ,  Yung-Chen Chien ,  Jerry Chang Jui Kao ,  Huang-Yu Chen ,  Chung-Hsing Wang

IPC分类号： H01L27/02 ,  H01L27/092 ,  G06F30/394 ,  H01L21/8238 ,  G06F30/392 ,  H01L23/522

CPC分类号： H01L27/0207 ,  G06F30/392 ,  G06F30/394 ,  H01L21/823871 ,  H01L23/5226 ,  H01L27/092

摘要： An integrated circuit (IC) device includes a substrate, and a cell over the substrate. The cell includes at least one active region and at least one gate region extending across the at least one active region. The cell further includes at least one input/output (IO) pattern configured to electrically couple one or more of the at least one active region and the at least one gate region to external circuitry outside the cell. The at least one IO pattern extends obliquely to both the at least one active region and the at least one gate region.

公开(公告)号：US11151297B2

公开(公告)日：2021-10-19

申请号：US17065086

申请日：2020-10-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Po-Chia Lai ,  Ming-Chang Kuo ,  Jerry Chang Jui Kao ,  Wei-Ling Chang ,  Wei-Ren Chen ,  Hui-Zhong Zhuang ,  Stefan Rusu ,  Lee-Chung Lu

IPC分类号： G06F30/392 ,  G06F119/06

摘要： A method includes positioning adjacent first through fourth active regions in a cell of an IC layout diagram, the first active region being a first type of an n-type or a p-type and corresponding to a first total number of fins, the second active region being a second type of the n-type or the p-type and corresponding to a second total number of fins, the third active region being the second type and corresponding to a third total number of fins, and the fourth active region being the first type and corresponding to a fourth total number of fins. Each of the first and second total numbers of fins is greater than each of the third and fourth total numbers of fins, and at least one of the positioning the first, second, third, or fourth active regions is performed by a processor.