-
公开(公告)号：US11417588B2
公开(公告)日：2022-08-16
申请号：US16943806
申请日：2020-07-30
摘要： A semiconductor structure includes a plurality of vias and a metal layer. The vias disposed on a semiconductor substrate. The metal layer has a plurality of metal lines and at least one transmission gate line region. The metal lines are connected to the vias. The at least one transmission gate line region is connected to at least one transmission gate corresponding to at least one transmission gate circuit. The transmission gate line region includes at least one different-net via pair. The different-net via pair has two metal lines and each of the two metal lines is connected to a via respectively. The two metal lines extend along a first axis but toward opposite directions. A distance between the two vias of the different-net via pair is within about 1.5 poly pitch.
-
公开(公告)号：US20240063211A1
公开(公告)日：2024-02-22
申请号：US18447999
申请日：2023-08-10
发明人： Wei-Ling Chang , Jung-Chan Yang , Li-Chun Tien , Ting Yu Chen
IPC分类号： H01L27/02 , H01L21/8234 , H01L27/088 , H03K19/17772
CPC分类号： H01L27/0207 , H01L21/823431 , H01L21/823475 , H01L27/0886 , H03K19/17772
摘要： A power gating cell on an integrated circuit is provided. The power gating cell includes: a central area; a peripheral area surrounding the central area; a first active region located in the central area, the first active region having a first width in a first direction corresponding to at least four fin structures extending in a second direction perpendicular to the first direction; and a plurality of second active regions located in the peripheral area, each second active region having a second width in the first direction corresponding to at least one and no more than three fin structures extending in the second direction.
-
公开(公告)号：US11151297B2
公开(公告)日：2021-10-19
申请号：US17065086
申请日：2020-10-07
发明人： Po-Chia Lai , Ming-Chang Kuo , Jerry Chang Jui Kao , Wei-Ling Chang , Wei-Ren Chen , Hui-Zhong Zhuang , Stefan Rusu , Lee-Chung Lu
IPC分类号： G06F30/392 , G06F119/06
摘要： A method includes positioning adjacent first through fourth active regions in a cell of an IC layout diagram, the first active region being a first type of an n-type or a p-type and corresponding to a first total number of fins, the second active region being a second type of the n-type or the p-type and corresponding to a second total number of fins, the third active region being the second type and corresponding to a third total number of fins, and the fourth active region being the first type and corresponding to a fourth total number of fins. Each of the first and second total numbers of fins is greater than each of the third and fourth total numbers of fins, and at least one of the positioning the first, second, third, or fourth active regions is performed by a processor.
-
公开(公告)号：US11862620B2
公开(公告)日：2024-01-02
申请号：US17021045
申请日：2020-09-15
发明人： Wei-Ling Chang , Jung-Chan Yang , Li-Chun Tien , Ting Yu Chen
IPC分类号： H01L23/528 , H01L27/02 , H01L21/8234 , H01L27/088 , H03K19/17772
CPC分类号： H01L27/0207 , H01L21/823431 , H01L21/823475 , H01L27/0886 , H03K19/17772
摘要： A power gating cell on an integrated circuit is provided. The power gating cell includes: a central area; a peripheral area surrounding the central area; a first active region located in the central area, the first active region having a first width in a first direction corresponding to at least four fin structures extending in a second direction perpendicular to the first direction; and a plurality of second active regions located in the peripheral area, each second active region having a second width in the first direction corresponding to at least one and no more than three fin structures extending in the second direction.
-
公开(公告)号：US11682671B2
公开(公告)日：2023-06-20
申请号：US17037447
申请日：2020-09-29
发明人： Wei-Ling Chang , Lee-Chung Lu , Xiangdong Chen , Kam-Tou Sio , Hsiang-Chi Huang
IPC分类号： H01L21/8238 , H01L27/092 , H01L23/528 , H01L29/08 , H01L21/28 , H01L29/49
CPC分类号： H01L27/092 , H01L21/28123 , H01L21/823828 , H01L21/823871 , H01L23/528 , H01L29/0847 , H01L29/4916
摘要： An integrated circuit structure includes a first transistor, a second transistor, a first conductive via, a second conductive via, and a connection line. The first transistor includes a first active region, a first gate electrode over the first active region; and a first channel in the first active region and under the first gate electrode. The second transistor includes a second active region, a second gate electrode over the second active region, and a second channel in the second active region and under the second gate electrode. The first conductive via is electrically connected to the first gate electrode. The second conductive via is electrically connected to the second gate electrode. The connection line electrically connects the first and second conductive vias. The first transistor and the first conductive via and the second transistor and the second conductive via are arranged mirror-symmetrically with respect to a symmetry plane.
-
公开(公告)号：US11275885B2
公开(公告)日：2022-03-15
申请号：US17081438
申请日：2020-10-27
发明人： Shun Li Chen , Li-Chun Tien , Ting Yu Chen , Wei-Ling Chang
IPC分类号： G06F30/398 , G06F30/392 , G06F30/394 , G06F30/3947 , G06F30/3953 , H01L21/70 , H01L25/00 , H03K19/00 , G03F1/36
摘要： A semiconductor cell structure includes four transistors, two gate-strips, four pairs of conductive segments, and a plurality of horizontal routing lines. Each of the two gate-strips intersects a first-type active zone and a second-type active zone. A first conductive segment is configured to have a first supply voltage. A second conductive segment is configured to have a second supply voltage. The first gate-strip is conductively connected to the second conductive segment. Each of the horizontal routing lines intersects one or more conductive segments over one or more corresponding intersections while conductively isolated from the one or more conductive segments at each of the one or more corresponding intersections.
-
公开(公告)号：US20230369320A1
公开(公告)日：2023-11-16
申请号：US18182657
申请日：2023-03-13
发明人： Ya-Chi Chou , Wei-Ling Chang , Wei-Ren Chen , Chi-Yu Lu
IPC分类号： H01L27/088 , H01L27/092 , H01L21/762
CPC分类号： H01L27/088 , H01L27/092 , H01L21/76224
摘要： A device includes a substrate, a first well region, a second well region, and a dummy region in the substrate, where the dummy region is a non-functional region situated between the first well region and the second well region. The first well region is configured to receive a first voltage and the second well region is configured to receive a second voltage that is different than the first voltage. The device further includes an active region that extends through at least part of the first well region and at least part of the dummy region, and at least one isolation structure situated in the dummy region between a first gate structure that extends over the active region in the dummy region on one side of the at least one isolation structure and a second gate structure on another side of the at least one isolation structure.
-
公开(公告)号：US11916017B2
公开(公告)日：2024-02-27
申请号：US17446022
申请日：2021-08-26
发明人： Wei-Ling Chang , Chih-Liang Chen , Chia-Tien Wu , Guo-Huei Wu
IPC分类号： H01L23/528 , H01L21/8238 , H01L23/522
CPC分类号： H01L23/528 , H01L21/823871 , H01L23/5226
摘要： An integrated circuit includes a plurality of horizontal conducting lines in a first connection layer, a plurality of gate-conductors below the first connection layer, a plurality of terminal-conductors below the first connection layer, and a via-connector directly connecting one of the horizontal conducting lines with one of the gate-conductors or with one of the terminal-conductors. The integrated circuit also includes a plurality of vertical conducting lines in a second connection layer above the first connection layer, and a plurality of pin-connectors for a circuit cell. A first pin-connector is directly connected between a first horizontal conducting line and a first vertical conducting line atop one of the gate-conductors. A second pin-connector is directly connected between a second horizontal conducting line and a second vertical conducting line atop a vertical boundary of the circuit cell.
-
公开(公告)号：US11675961B2
公开(公告)日：2023-06-13
申请号：US17670370
申请日：2022-02-11
发明人： Shun Li Chen , Li-Chun Tien , Ting Yu Chen , Wei-Ling Chang
IPC分类号： G06F30/398 , G06F30/392 , G06F30/394 , G06F30/3947 , G06F30/3953 , G03F1/36 , H01L21/70 , H01L25/00 , H03K19/00
CPC分类号： G06F30/398 , G03F1/36 , G06F30/392 , G06F30/394 , G06F30/3947 , G06F30/3953 , H01L21/70 , H01L25/00 , H03K19/00
摘要： A semiconductor cell structure includes four pairs of conductive segments, a first gate-strip, and a second gate-strip. A first conductive segment is configured to have a first supply voltage, and a second conductive segment is configured to have a second supply voltage. Each of the first gate-strip and the second gate-strip intersects an active zone over a channel region of a transistor. The first gate-strip is conductively connected to the second conductive segment. The semiconductor cell structure also includes a first dummy gate-strip and a second dummy gate-strip. The first dummy gate-strip separates from the first gate-strip by one CPP. The second dummy gate-strip separates from the second gate-strip by one CPP. The first gate-strip and the second gate-strip are separated from each other by two CPPs. The dummy gate-strip and the second dummy gate-strip are separated from each other by four CPPs.
-
公开(公告)号：US20220085005A1
公开(公告)日：2022-03-17
申请号：US17021045
申请日：2020-09-15
发明人： Wei-Ling Chang , Jung-Chan Yang , Li-Chun Tien , Ting Yu Chen
IPC分类号： H01L27/02 , H01L27/088 , H03K19/17772 , H01L21/8234
摘要： A power gating cell on an integrated circuit is provided. The power gating cell includes: a central area; a peripheral area surrounding the central area; a first active region located in the central area, the first active region having a first width in a first direction corresponding to at least four fin structures extending in a second direction perpendicular to the first direction; and a plurality of second active regions located in the peripheral area, each second active region having a second width in the first direction corresponding to at least one and no more than three fin structures extending in the second direction.
-
-
-
-
-
-
-
-
-
搜索结果
10 条记录 (耗时 0.016 秒)
