公开(公告)号：US20180233522A1

公开(公告)日：2018-08-16

申请号：US15954305

申请日：2018-04-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Victor Chiang LIANG ,  Fu-Huan TSAI ,  Fang-Ting KUO ,  Meng-Chang HO ,  Yu-Lin WEI ,  Chi-Feng HUANG

IPC: H01L27/146 ,  H01L29/93 ,  H01L29/66 ,  H01L27/07

CPC classification number: H01L27/14603 ,  H01L27/0733 ,  H01L27/14614 ,  H01L27/1463 ,  H01L27/14689 ,  H01L29/66174 ,  H01L29/93

Abstract: A semiconductor device includes a substrate, wherein the substrate includes a channel region. The semiconductor device further includes an isolation feature in the substrate. The isolation feature includes a first portion in the substrate, and a second portion extending along a top surface of the substrate. The second portion partially covers the channel region. The semiconductor device further includes a gate structure over the substrate, wherein the gate structure partially covers the second portion of the isolation feature.

公开(公告)号：US20240296268A1

公开(公告)日：2024-09-05

申请号：US18337262

申请日：2023-06-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Fong-Yuan CHANG ,  Hui Yu LEE ,  Yu-Hao CHEN ,  Tian-Jian WU ,  Tien-Chien HUANG ,  Manjo Kumar ENUGULA ,  Yu-Lin WEI ,  Jyun-Hao CHANG

IPC: G06F30/31 ,  G06F30/323 ,  G06F30/327

CPC classification number: G06F30/31 ,  G06F30/323 ,  G06F30/327

Abstract: A method includes tagging source PDK devices (SPDs) in a source-circuit design (SCD); generating a source design simulation database (SDSD) based on source design key performance indicator (KPI) simulation data of the SPDs in the SCD; generating a target process design kit (PDK) simulation database (TPSD) based on target design KPI simulation data of a plurality of target-PDK devices (TPDs); creating a matching table based on the SDSD and the TPSD; matching, based on the matching table, one or more TPDs from the TPSD with each SPD in the SDSD based on SPD KPIs; ranking the one or more TPDs matched from the TPSD with each SPD in the SDSD based on the SPD KPIs; and exchanging, based on a migration mapping table that includes a one-to-one relationship for TPDs to the SPDs in the SCD, one or more SPDs in the SCD with one-to-one relational TPDs.

公开(公告)号：US20200152676A1

公开(公告)日：2020-05-14

申请号：US16738887

申请日：2020-01-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Victor Chiang LIANG ,  Fu-Huan TSAI ,  Fang-Ting KUO ,  Meng-Chang HO ,  Yu-Lin WEI ,  Chi-Feng HUANG

IPC: H01L27/146 ,  H01L29/66 ,  H01L27/07 ,  H01L29/93

Abstract: A method of making a semiconductor device includes etching a substrate to define a trench in a substrate, wherein the trench is adjacent to an active region in the substrate, and etching the substrate includes patterning a mask. The method further includes partially removing the mask to expose a first portion of the active region, wherein the first portion extends a first distance from the trench. The method further includes depositing a dielectric material to fill the trench and cover the first portion of the active region. The method further includes removing the mask, wherein the removing of the mask includes maintaining the dielectric material covering the first portion of the active region. The method further includes forming a gate structure over the active region and over the dielectric material.

公开(公告)号：US20210351210A1

公开(公告)日：2021-11-11

申请号：US17384355

申请日：2021-07-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Victor Chiang LIANG ,  Fu-Huan TSAI ,  Chi-Feng HUANG ,  Yu-Lin WEI ,  Fang-Ting KUO ,  Meng-Chang HO

IPC: H01L27/146 ,  H01L29/66 ,  H01L27/07 ,  H01L29/93

Abstract: A low noise device includes an isolation feature in a substrate. The low noise device further includes a gate stack over a channel in the substrate, wherein the isolation feature is adjacent to the channel. The low noise device further includes a spacer surrounding a portion of the gate stack, wherein an edge of the gate stack is spaced from an edge of the isolation feature adjacent to the spacer by a distance ranging from a minimum spacing distance to about 0.3 microns (μm).

公开(公告)号：US20170345855A1

公开(公告)日：2017-11-30

申请号：US15428356

申请日：2017-02-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Victor Chiang LIANG ,  Fu-Huan TSAI ,  Fang-Ting KUO ,  Meng-Chang HO ,  Yu-Lin WEI ,  Chi-Feng HUANG

IPC: H01L27/146 ,  H01L29/93 ,  H01L27/07

CPC classification number: H01L27/14603 ,  H01L27/0733 ,  H01L27/14614 ,  H01L27/1463 ,  H01L27/14689 ,  H01L29/66174 ,  H01L29/93

Abstract: A low noise device includes an isolation feature in a substrate. The low noise device further includes a gate stack over a channel in the substrate. The gate stack includes a gate dielectric layer extending over a portion of the isolation feature, and a gate electrode over the gate dielectric layer. The low noise device further includes a charge trapping reducing structure adjacent to the isolation feature. The charge trapping reducing structure is configured to reduce a number of charge carriers adjacent an interface between the isolation feature and the channel.