公开(公告)号：US20240234566A1

公开(公告)日：2024-07-11

申请号：US18150206

申请日：2023-01-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： LING MEI LIN ,  YU-CHANG JONG ,  CHIH-HSIUNG HUANG ,  YU-HSIEN CHU ,  WEN-CHIH CHIANG ,  CHIH-MING LEE ,  CHENG-MING WU ,  PEI-LUN WANG

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7801 ,  H01L21/0206 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02255 ,  H01L21/02263 ,  H01L21/02304 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31105 ,  H01L21/31144 ,  H01L29/0611 ,  H01L29/0852 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/66674

Abstract: A method includes: forming a barrier layer in a substrate; depositing a first dielectric layer over the substrate; forming a patterned mask layer over the first dielectric layer;
patterning the first dielectric layer into a first sublayer of a gate dielectric layer;
converting at least part of the patterned mask layer into a second sublayer of the gate dielectric layer; depositing a second dielectric layer adjacent to the first and second sublayers to serve as a third sublayer of the gate dielectric layer; and depositing a gate electrode over the gate dielectric layer.