公开(公告)号：US20150364420A1

公开(公告)日：2015-12-17

申请号：US14305356

申请日：2014-06-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： LING MEI LIN ,  CHUN LI WU ,  YU-PIN CHANG

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/05 ,  H01L2224/48091 ,  H01L2224/48453 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: In some embodiments, an interconnect structure includes a base layer, a plurality of dielectric layers and a conductive structure. The base layer includes a conductive region. The plurality of dielectric layers are formed over the base layer. The plurality of dielectric layers includes a first dielectric layer and an etch stop layer under the first dielectric layer. The conductive structure includes a plug. The plug includes a central region and one or more footing regions. The footing regions are formed around the central region and formed at least partially in the first etch stop layer. A total width of the central region and one or more footing regions at a bottom level of the plurality of dielectric layers is at least about 5% more than a width of the central region at the bottom level of the plurality of dielectric layers.

Abstract translation: 在一些实施例中，互连结构包括基底层，多个电介质层和导电结构。 基层包括导电区域。 多个电介质层形成在基底层上。 多个电介质层包括在第一介电层下面的第一介电层和蚀刻停止层。 导电结构包括插头。 插头包括中心区域和一个或多个基脚区域。 基部区域围绕中心区域形成并至少部分地形成在第一蚀刻停止层中。 多个介电层的底部高度处的中心区域和一个或多个基脚区域的总宽度比多个介电层底部的中心区域的宽度大至少约5％。

公开(公告)号：US20240234566A1

公开(公告)日：2024-07-11

申请号：US18150206

申请日：2023-01-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： LING MEI LIN ,  YU-CHANG JONG ,  CHIH-HSIUNG HUANG ,  YU-HSIEN CHU ,  WEN-CHIH CHIANG ,  CHIH-MING LEE ,  CHENG-MING WU ,  PEI-LUN WANG

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7801 ,  H01L21/0206 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02255 ,  H01L21/02263 ,  H01L21/02304 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31105 ,  H01L21/31144 ,  H01L29/0611 ,  H01L29/0852 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/66674

Abstract: A method includes: forming a barrier layer in a substrate; depositing a first dielectric layer over the substrate; forming a patterned mask layer over the first dielectric layer;
patterning the first dielectric layer into a first sublayer of a gate dielectric layer;
converting at least part of the patterned mask layer into a second sublayer of the gate dielectric layer; depositing a second dielectric layer adjacent to the first and second sublayers to serve as a third sublayer of the gate dielectric layer; and depositing a gate electrode over the gate dielectric layer.