公开(公告)号：US11855632B2

公开(公告)日：2023-12-26

申请号：US17115571

申请日：2020-12-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shao-Huan Wang ,  Chun-Chen Chen ,  Sheng-Hsiung Chen ,  Kuo-Nan Yang

IPC: H03K19/17704 ,  H01L23/528 ,  H03K19/17736 ,  H01L27/02 ,  G06F30/392

CPC classification number: H03K19/17704 ,  G06F30/392 ,  H01L23/528 ,  H01L27/0207 ,  H03K19/17736

Abstract: A logic cell structure includes a first portion, a second portion and a third portion. The first portion, arranged to be a first layout of a first semiconductor element, is placed in a first cell row of a substrate area extending in a first direction. The second portion, arranged to be a second layout of a second semiconductor element, is placed in a second cell row of the substrate area. The third portion is arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element. The first, second and third portions are bounded by a bounding box with a height in a second direction and a width in the first direction. Respective centers of the first portion and the second portion are arranged in a third direction different from each of the first direction and the second direction.

公开(公告)号：US11727185B2

公开(公告)日：2023-08-15

申请号：US17815013

申请日：2022-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shao-Huan Wang ,  Sheng-Hsiung Chen ,  Wen-Hao Chen ,  Chun-Chen Chen ,  Hung-Chih Ou

IPC: G06F30/394 ,  G06F30/20 ,  G06F30/327 ,  G06F30/392 ,  G06F30/3312 ,  G06F30/373 ,  G06F30/33 ,  G06F30/337 ,  G06F30/398 ,  H01L23/52 ,  H01L23/522 ,  G06F111/04 ,  G06F119/12

CPC classification number: G06F30/394 ,  G06F30/20 ,  G06F30/327 ,  G06F30/3312 ,  G06F30/392 ,  G06F30/33 ,  G06F30/337 ,  G06F30/373 ,  G06F30/398 ,  G06F2111/04 ,  G06F2119/12 ,  H01L23/5226

Abstract: A system includes a non-transitory computer readable medium configured to store instructions thereon. The system further includes a processor connected to the non-transitory computer readable medium. The processor is configured to execute the instruction for comparing a size of a via pillar structure of a first layout pattern of a plurality of layout patterns with a size of a via pillar structure of a second layout pattern of the plurality of layout patterns, wherein each of the plurality of layout patterns meets an electromigration (EM) rule. The processor is further configured to execute the instructions for replacing, in a layout design, the first layout pattern with the second layout pattern in response to the size of the via pillar structure of the second layout pattern being less than the size of the via pillar structure of the first layout pattern.

公开(公告)号：US11138360B2

公开(公告)日：2021-10-05

申请号：US16662827

申请日：2019-10-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Po-Hsiang Huang ,  Chin-Chou Liu ,  Sheng-Hsiung Chen ,  Fong-Yuan Chang ,  Hui-Zhong Zhuang ,  Meng-Hsueh Wang ,  Yi-Kan Cheng ,  Chun-Chen Chen

IPC: G06F30/392 ,  H01L23/528 ,  H01L23/522 ,  G06F30/394 ,  G06F30/398 ,  G06F119/18

Abstract: A method of generating a layout diagram including a first level of metallization (M_1st level) including: identifying, in the layout diagram, a filler cell and a first functional cell substantially abutting the filler cell; the first functional cell including first and second side boundaries, first wiring patterns in the M_1st level, and representing corresponding first conductors in the first functional cell region; and first and second groups of cut patterns overlying corresponding portions of the first wiring patterns and being substantially aligned with the corresponding first and second side boundaries; adjusting one or more locations of corresponding one or more selected cut patterns of the second group thereby correspondingly elongating one or more selected ones of the first wiring patterns so as to be corresponding first elongated wiring patterns which extend across the second boundary of the first functional cell into the filler cell.