公开(公告)号：US20240290652A1

公开(公告)日：2024-08-29

申请号：US18657752

申请日：2024-05-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Chung Chen ,  Chi-Feng Huang ,  Victor Chiang Liang ,  Chung-Hao Chu ,  Ching-Yu Yang

IPC: H01L21/768 ,  H01L21/324 ,  H01L29/08 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76814 ,  H01L21/324 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/665 ,  H01L29/6656

Abstract: A semiconductor device includes a first gate stack structure over a substrate, a source/drain epitaxial layer, a lightly doped region, and a silicide region. The source/drain epitaxial layer is disposed in the substrate and adjacent to the first gate stack structure. The lightly doped region is located in the substrate to be electrically connected to the source/drain epitaxial layer. The lightly doped region includes a first portion protrudes from a sidewall of the source/drain epitaxial layer. The silicide region is in contact with a top surface and sidewalls of a top portion of the source/drain epitaxial layer and a top surface of the first portion of the lightly doped region. The top portion of the source/drain epitaxial layer is higher than the top surface of the first portion of the lightly doped region.

公开(公告)号：US11862467B2

公开(公告)日：2024-01-02

申请号：US17839682

申请日：2022-06-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chia-Chung Chen ,  Chung-Hao Chu ,  Chi-Feng Huang ,  Victor Chiang Liang

IPC: H01L21/26 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/265 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of manufacturing a semiconductor structure, comprising providing a substrate; forming a fin structure over the substrate; depositing an insulation material over the fin structure; performing a plurality of ion implantation cycles in-situ with implantation energy increased or decreased stepwise; and removing at least a portion of the insulation material to expose a portion of the fin structure.

公开(公告)号：US20220367634A1

公开(公告)日：2022-11-17

申请号：US17876566

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Chung Chen ,  Chi-Feng Huang ,  Victor Chiang Liang ,  Chung-Hao Chu

IPC: H01L29/10 ,  H01L21/762 ,  H01L23/528 ,  H01L21/768

Abstract: Provided is a semiconductor device including a substrate having a lower portion and an upper portion on the lower portion; an isolation region disposed on the lower portion of the substrate and surrounding the upper portion of the substrate in a closed path; a gate structure disposed on and across the upper portion of the substrate; source and/or drain (S/D) regions disposed in the upper portion of the substrate at opposite sides of the gate structure; and a channel region disposed below the gate structure and abutting between the S/D regions, wherein the channel region and the S/D regions have different conductivity types, and the channel region and the substrate have the same conductivity type.

公开(公告)号：US20220359275A1

公开(公告)日：2022-11-10

申请号：US17874310

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Chung Chen ,  Chi-Feng Huang ,  Victor Chiang Liang ,  Chung-Hao Chu ,  Ching-Yu Yang

IPC: H01L21/768 ,  H01L29/08 ,  H01L29/165 ,  H01L29/45 ,  H01L29/78 ,  H01L21/324

Abstract: A semiconductor device includes a plurality of gate electrodes over a substrate, and a source/drain epitaxial layer. The source/drain epitaxial layer is disposed in the substrate and between two adjacent gate electrodes, wherein a bottom surface of the source/drain epitaxial layer is buried in the substrate to a depth less than or equal to two-thirds of a spacing between the two adjacent gate electrodes.

公开(公告)号：US11973113B2

公开(公告)日：2024-04-30

申请号：US17876566

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Chung Chen ,  Chi-Feng Huang ,  Victor Chiang Liang ,  Chung-Hao Chu

IPC: H01L29/76 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528 ,  H01L29/10 ,  H01L29/94

CPC classification number: H01L29/1033 ,  H01L21/76205 ,  H01L21/76224 ,  H01L21/76816 ,  H01L23/5283

Abstract: Provided is a semiconductor device including a substrate having a lower portion and an upper portion on the lower portion; an isolation region disposed on the lower portion of the substrate and surrounding the upper portion of the substrate in a closed path; a gate structure disposed on and across the upper portion of the substrate; source and/or drain (S/D) regions disposed in the upper portion of the substrate at opposite sides of the gate structure; and a channel region disposed below the gate structure and abutting between the S/D regions, wherein the channel region and the S/D regions have different conductivity types, and the channel region and the substrate have the same conductivity type.

公开(公告)号：US11996323B2

公开(公告)日：2024-05-28

申请号：US17874310

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Chung Chen ,  Chi-Feng Huang ,  Victor Chiang Liang ,  Chung-Hao Chu ,  Ching-Yu Yang

IPC: H01L21/768 ,  H01L21/324 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76814 ,  H01L21/324 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/665 ,  H01L29/6656

Abstract: A semiconductor device includes a plurality of gate electrodes over a substrate, and a source/drain epitaxial layer. The source/drain epitaxial layer is disposed in the substrate and between two adjacent gate electrodes, wherein a bottom surface of the source/drain epitaxial layer is buried in the substrate to a depth less than or equal to two-thirds of a spacing between the two adjacent gate electrodes.

公开(公告)号：US11380548B2

公开(公告)日：2022-07-05

申请号：US16883955

申请日：2020-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chia-Chung Chen ,  Chung-Hao Chu ,  Chi-Feng Huang ,  Victor Chiang Liang

IPC: H01L21/26 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor structure, comprising providing a substrate; forming a fin structure over the substrate; depositing an insulation material over the fin structure; performing a plurality of ion implantations in-situ with implantation energy increased or decreased stepwise; and removing at least a portion of the insulation material to expose a portion of the fin structure.

公开(公告)号：US11264486B2

公开(公告)日：2022-03-01

申请号：US16744811

申请日：2020-01-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chung-Hao Chu ,  Chia-Chung Chen ,  Shu Fang Fu ,  Chi-Feng Huang ,  Victor Chiang Liang

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: The present disclosure provides a semiconductor device, including a substrate, a fin over the substrate, wherein the fin extends along a primary direction, a gate over the fin, the gate extends along the secondary direction orthogonal to the primary direction, a first conductive contact over the gate, and a conductive routing layer over the first conductive contact, wherein at least a portion of the fin is free from the coverage of a vertical projection of the conductive routing layer.