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公开(公告)号：US11996323B2
公开(公告)日：2024-05-28
申请号：US17874310
申请日：2022-07-27
IPC分类号： H01L21/768 , H01L21/324 , H01L29/08 , H01L29/10 , H01L29/165 , H01L29/45 , H01L29/66 , H01L29/78
CPC分类号： H01L21/76814 , H01L21/324 , H01L21/76805 , H01L21/76843 , H01L21/76895 , H01L29/0847 , H01L29/165 , H01L29/45 , H01L29/7833 , H01L29/7848 , H01L29/665 , H01L29/6656
摘要： A semiconductor device includes a plurality of gate electrodes over a substrate, and a source/drain epitaxial layer. The source/drain epitaxial layer is disposed in the substrate and between two adjacent gate electrodes, wherein a bottom surface of the source/drain epitaxial layer is buried in the substrate to a depth less than or equal to two-thirds of a spacing between the two adjacent gate electrodes.
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公开(公告)号：US11936299B2
公开(公告)日：2024-03-19
申请号：US17027032
申请日：2020-09-21
发明人： Chu Fu Chen , Chi-Feng Huang , Chia-Chung Chen , Chin-Lung Chen , Victor Chiang Liang , Chia-Cheng Pao
IPC分类号： H02M3/158 , H01L21/84 , H01L29/08 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/80 , H01L21/265
CPC分类号： H02M3/1582 , H01L21/84 , H01L29/0847 , H01L29/4232 , H01L29/66659 , H01L29/7835 , H01L29/7836 , H01L29/80 , H01L21/26586 , H02M3/158
摘要： A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region. The transistor further includes a source/drain (S/D) in the substrate adjacent to the gate structure. The transistor further includes a lightly doped drain (LDD) region adjacent to the S/D, wherein a dopant concentration in the first LDD is less than a dopant concentration in the S/D. The transistor further includes a doping extension region adjacent the LDD region, wherein the doping extension region extends farther under the gate structure than the LDD region, and a maximum depth of the doping extension region is 10-times to 30-times greater than a maximum depth of the LDD.
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3.发明授权公开(公告)号：US11380548B2
公开(公告)日：2022-07-05
申请号：US16883955
申请日：2020-05-26
IPC分类号： H01L21/26 , H01L21/265 , H01L21/8234 , H01L29/78 , H01L29/66
摘要： A method of manufacturing a semiconductor structure, comprising providing a substrate; forming a fin structure over the substrate; depositing an insulation material over the fin structure; performing a plurality of ion implantations in-situ with implantation energy increased or decreased stepwise; and removing at least a portion of the insulation material to expose a portion of the fin structure.
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公开(公告)号：US11264486B2
公开(公告)日：2022-03-01
申请号：US16744811
申请日：2020-01-16
IPC分类号： H01L21/00 , H01L29/66 , H01L21/8234 , H01L29/78
摘要： The present disclosure provides a semiconductor device, including a substrate, a fin over the substrate, wherein the fin extends along a primary direction, a gate over the fin, the gate extends along the secondary direction orthogonal to the primary direction, a first conductive contact over the gate, and a conductive routing layer over the first conductive contact, wherein at least a portion of the fin is free from the coverage of a vertical projection of the conductive routing layer.
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公开(公告)号：US10854708B2
公开(公告)日：2020-12-01
申请号：US16682381
申请日：2019-11-13
发明人： Chewn-Pu Jou , Chih-Hsin Ko , Po-Wen Chiu , Chao-Ching Cheng , Chun-Chieh Lu , Chi-Feng Huang , Huan-Neng Chen , Fu-Lung Hsueh , Clement Hsingjen Wann
IPC分类号： H01L49/02 , H01L23/528 , H01G4/008 , H01G4/005 , H01L23/522 , H01L23/532 , H01L21/768
摘要： A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers.
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公开(公告)号：US10453809B2
公开(公告)日：2019-10-22
申请号：US15495077
申请日：2017-04-24
发明人： Chia-Chung Chen , Chi-Feng Huang , Shu Fang Fu , Tzu-Jin Yeh , Chewn-Pu Jou
IPC分类号： H01L21/762 , H01L29/417 , H01L29/78 , H01L21/761 , H01L23/66 , H01L29/66 , H01L29/10 , H01L21/265 , H01L27/06 , H01L49/02 , H01L29/06 , H01L29/45
摘要： A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch.
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公开(公告)号：US09947701B2
公开(公告)日：2018-04-17
申请号：US15428356
申请日：2017-02-09
发明人： Victor Chiang Liang , Fu-Huan Tsai , Fang-Ting Kuo , Meng-Chang Ho , Yu-Lin Wei , Chi-Feng Huang
IPC分类号： H01L27/108 , H01L27/146 , H01L27/07 , H01L29/93
CPC分类号： H01L27/14603 , H01L27/0733 , H01L27/14614 , H01L27/1463 , H01L27/14689 , H01L29/66174 , H01L29/93
摘要： A low noise device includes an isolation feature in a substrate. The low noise device further includes a gate stack over a channel in the substrate. The gate stack includes a gate dielectric layer extending over a portion of the isolation feature, and a gate electrode over the gate dielectric layer. The low noise device further includes a charge trapping reducing structure adjacent to the isolation feature. The charge trapping reducing structure is configured to reduce a number of charge carriers adjacent an interface between the isolation feature and the channel.
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公开(公告)号：US20170229406A1
公开(公告)日：2017-08-10
申请号：US15495077
申请日：2017-04-24
发明人： Chia-Chung Chen , Chi-Feng Huang , Shu Fang Fu , Tzu-Jin Yeh , Chewn-Pu Jou
摘要： A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch.
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公开(公告)号：US09478659B2
公开(公告)日：2016-10-25
申请号：US14310333
申请日：2014-06-20
IPC分类号： H01L27/092 , H01L27/12 , H01L27/108 , H01L29/66 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/26513 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/10879 , H01L27/1211 , H01L29/66787 , H01L29/785
摘要： A transistor includes a substrate having an upper surface, a fin structure protruding from the upper surface of the substrate, an isolation structure over the upper surface of the substrate and surrounding a lower portion of the fin structure, and a first doped region at least partially embedded in an upper portion of the fin structure. The fin structure extends along a first direction. The first doped region has a first type doping different from that of the fin structure.
摘要翻译： 晶体管包括具有上表面的衬底，从衬底的上表面突出的鳍结构，在衬底的上表面上并围绕鳍结构的下部的隔离结构，以及至少部分地形成第一掺杂区 嵌入翅片结构的上部。 翅片结构沿着第一方向延伸。 第一掺杂区具有不同于鳍结构的第一掺杂区。
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公开(公告)号：US09184256B2
公开(公告)日：2015-11-10
申请号：US14263744
申请日：2014-04-28
发明人： Chi-Feng Huang , Chia-Chung Chen
IPC分类号： H01L27/088 , H01L29/66 , H01L29/93 , H01L29/94 , H01L27/08
CPC分类号： H01L29/66174 , H01L27/0808 , H01L27/0811 , H01L29/93 , H01L29/94
摘要： Apparatus and methods for a MOS varactor structure are disclosed. An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed.
摘要翻译： 公开了MOS变容二极管结构的装置和方法。 提供了一种装置，包括限定在半导体衬底的一部分中的有源区; 在有源区域中延伸到半导体衬底中的掺杂阱区; 在所述掺杂阱区域上平行布置的至少两个栅极结构; 源极和漏极区域，设置在形成在栅极结构的相对侧上的阱区域中; 栅极连接器，形成在覆盖所述至少两个栅极结构并电耦合所述至少两个栅极结构的第一金属层中; 源极和漏极连接器，其形成在第二金属层中并电耦合到源极和漏极区域; 以及将第二金属层中的源极和漏极连接器与形成在第一金属层中的栅极连接器分开的层间电介质材料。 公开了形成结构的方法。
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