公开(公告)号：US20150206946A1

公开(公告)日：2015-07-23

申请号：US14530320

申请日：2014-10-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： I-CHIH CHEN ,  FU-TSUN TSAI ,  YUNG-FA LEE ,  KO-MIN LIN ,  CHIH-MU HUANG ,  YING-LANG WANG

IPC: H01L29/417 ,  H01L29/45 ,  H01L21/324 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/285

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/76814 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7848

Abstract: A semiconductor device includes a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; and an interconnect plug on the doped region. The raised source/drain region includes a top surface being elevated from a surface of the substrate; and a doped region exposed on the top surface. The doped region includes a dopant concentration greater than any other portions of the raised source/drain region. A bottommost portion of the interconnect plug includes a width approximate to a width of the doped region.

Abstract translation: 半导体器件包括在衬底上的栅极结构; 与栅极结构相邻的凸起的源极/漏极区域; 以及掺杂区域上的互连插头。 升高的源极/漏极区域包括从衬底的表面升高的顶表面; 以及暴露在顶表面上的掺杂区域。 掺杂区域包括大于凸起源极/漏极区域的任何其它部分的掺杂剂浓度。 互连插头的最底部包括近似于掺杂区域的宽度的宽度。

公开(公告)号：US20150137247A1

公开(公告)日：2015-05-21

申请号：US14081517

申请日：2013-11-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： I-CHIH CHEN ,  YING-LANG WANG ,  CHIH-MU HUANG ,  YING-HAO CHEN ,  WEN-CHANG KUO ,  JUNG-CHI JENG

IPC: H01L29/10 ,  H01L27/12 ,  H01L29/78 ,  H01L21/84 ,  H01L29/08 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/7833 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0928 ,  H01L29/161 ,  H01L29/6659

Abstract: A semiconductor device includes a p-type metal oxide semiconductor device (PMOS) and an n-type metal oxide semiconductor device (NMOS) disposed over a substrate. The PMOS has a first gate structure located on the substrate, a carbon doped n-type well disposed under the first gate structure, a first channel region disposed in the carbon doped n-type well, and activated first source/drain regions disposed on opposite sides of the first channel region. The NMOS has a second gate structure located on the substrate, a carbon doped p-type well disposed under the second gate structure, a second channel region disposed in the carbon doped p-type well, and activated second source/drain regions disposed on opposite sides of the second channel region.

Abstract translation: 半导体器件包括设置在衬底上的p型金属氧化物半导体器件（PMOS）和n型金属氧化物半导体器件（NMOS）。 PMOS具有位于衬底上的第一栅极结构，设置在第一栅极结构下方的掺杂碳的n型阱，设置在碳掺杂n型阱中的第一沟道区，以及设置在相反的第一栅极结构的激活的第一源极/漏极区 第一个渠道区域的边。 NMOS具有位于衬底上的第二栅极结构，设置在第二栅极结构下方的掺杂碳的p型阱，设置在碳掺杂p型阱中的第二沟道区，以及布置在相对的第二栅极结构中的激活的第二源极/漏极区 第二通道区域的侧面。

公开(公告)号：US20160111536A1

公开(公告)日：2016-04-21

申请号：US14515225

申请日：2014-10-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： I-CHIH CHEN ,  CHIH-MING HSIEH ,  FU-TSUN TSAI ,  YUNG-FA LEE ,  CHIH-MU HUANG

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/265 ,  H01L21/324 ,  H01L29/7848 ,  H01L29/785

Abstract: Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device including receiving a FinFET precursor including a fin structure formed between isolation regions, and a gate structure formed over a portion of the fin structure such that a sidewall of the fin structure is in contact with a gate spacer of the gate structure; patterning the fin structure to comprise a pattern of at least one upward step rising from the isolation region; forming a capping layer over the fin structure, the isolation region, and the gate structure; performing an annealing process on the FinFET precursor to form at least two dislocations along the upward step; and removing the capping layer.

Abstract translation: 本公开的一些实施例提供一种制造半导体器件的方法，该半导体器件包括接收包括形成在隔离区域之间的鳍结构的FinFET前体，以及形成在鳍结构的一部分上的栅极结构，使得翅片结构的侧壁处于 与栅极结构的栅极间隔物接触; 图案化鳍结构以包括从隔离区域上升的至少一个向上步骤的图案; 在鳍结构，隔离区和栅结构之上形成覆盖层; 对FinFET前体进行退火处理以沿着向上的台阶形成至少两个位错; 并去除覆盖层。

公开(公告)号：US20160380085A1

公开(公告)日：2016-12-29

申请号：US15260986

申请日：2016-09-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： I-CHIH CHEN ,  CHIH-MING HSIEH ,  FU-TSUN TSAI ,  YUNG-FA LEE ,  CHIH-MU HUANG

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/265 ,  H01L21/324 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of manufacturing a semiconductor device includes receiving a FinFET precursor including a fin structure formed between some isolation regions, and a gate structure formed over a portion of the fin structure; removing a top portion of the fin structure on either side of the gate structure; growing a semiconductive layer on top of a remaining portion of the fin structure such that a plurality of corners is formed over the fin structure; forming a capping layer over the semiconductive layer; performing an annealing process on the FinFET precursor to form a plurality of dislocations proximate to the corners; and removing the capping layer.

Abstract translation: 制造半导体器件的方法包括：接收FinFET前体，其包括在一些隔离区之间形成的鳍结构，以及形成在所述鳍结构的一部分上的栅极结构; 去除栅极结构两侧的翅片结构的顶部; 在翅片结构的剩余部分的顶部上生长半导体层，使得在翅片结构上方形成多个角部; 在所述半导体层上形成覆盖层; 对FinFET前体进行退火处理以形成靠近角部的多个位错; 并去除覆盖层。

公开(公告)号：US20150206945A1

公开(公告)日：2015-07-23

申请号：US14158643

申请日：2014-01-17

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： I-CHIH CHEN ,  CHIH-MU HUANG ,  LING-SUNG WANG ,  YING-HAO CHEN ,  WEN-CHANG KUO ,  JUNG-CHI JENG

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/324 ,  H01L29/78 ,  H01L29/45 ,  H01L29/08 ,  H01L21/285

CPC classification number: H01L29/41783 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/324 ,  H01L21/76804 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a metal oxide semiconductor device disposed over a substrate and an interconnect plug. The metal oxide semiconductor device includes a gate structure located on the substrate and a raised source/drain region disposed adjacent to the gate structure. The raised source/drain region includes a top surface above a surface of the substrate by a distance. The interconnect plug connects to the raised source/drain region. The interconnect plug includes a doped region contacting the top surface of the raised source/drain region, a metal silicide region located on the doped region, and a metal region located on the metal silicide region.

Abstract translation: 半导体器件包括设置在衬底上的金属氧化物半导体器件和互连插塞。 金属氧化物半导体器件包括位于衬底上的栅极结构和邻近栅极结构设置的升高的源极/漏极区域。 凸起的源极/漏极区域包括在衬底的表面上方一定距离的顶表面。 互连插头连接到凸起的源极/漏极区域。 互连插头包括接触凸起源极/漏极区域的顶表面的掺杂区域，位于掺杂区域上的金属硅化物区域和位于金属硅化物区域上的金属区域。