公开(公告)号：US20160380085A1

公开(公告)日：2016-12-29

申请号：US15260986

申请日：2016-09-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： I-CHIH CHEN ,  CHIH-MING HSIEH ,  FU-TSUN TSAI ,  YUNG-FA LEE ,  CHIH-MU HUANG

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/265 ,  H01L21/324 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of manufacturing a semiconductor device includes receiving a FinFET precursor including a fin structure formed between some isolation regions, and a gate structure formed over a portion of the fin structure; removing a top portion of the fin structure on either side of the gate structure; growing a semiconductive layer on top of a remaining portion of the fin structure such that a plurality of corners is formed over the fin structure; forming a capping layer over the semiconductive layer; performing an annealing process on the FinFET precursor to form a plurality of dislocations proximate to the corners; and removing the capping layer.

Abstract translation: 制造半导体器件的方法包括：接收FinFET前体，其包括在一些隔离区之间形成的鳍结构，以及形成在所述鳍结构的一部分上的栅极结构; 去除栅极结构两侧的翅片结构的顶部; 在翅片结构的剩余部分的顶部上生长半导体层，使得在翅片结构上方形成多个角部; 在所述半导体层上形成覆盖层; 对FinFET前体进行退火处理以形成靠近角部的多个位错; 并去除覆盖层。

公开(公告)号：US20150228720A1

公开(公告)日：2015-08-13

申请号：US14178814

申请日：2014-02-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： CHEN-CHUN CHEN ,  CHIU-JUNG CHEN ,  FU-TSUN TSAI ,  SHIU-KO JANGJIAN ,  CHI-CHERNG JENG ,  HSIN-CHI CHEN

IPC: H01L29/06 ,  H01L21/02 ,  H01L23/00

CPC classification number: H01L24/83 ,  H01L21/02019 ,  H01L21/0273 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/76256 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/1469 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/83201 ,  H01L2224/838 ,  H01L2224/83805 ,  H01L2224/8385 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2924/07025

Abstract: A semiconductor structure includes a wafer including a first surface and a periphery, a plurality of protrusions protruded from the first surface and a plurality of recesses spaced from each other by the plurality of protrusions, and each of the plurality of recesses is extended from the periphery of the wafer and is elongated across the first surface of the wafer.

Abstract translation: 半导体结构包括：第一表面和周边的晶片，从第一表面突出的多个突起和由多个突起彼此间隔开的多个凹部，并且多个凹部中的每一个从周边延伸 并且延伸穿过晶片的第一表面。

公开(公告)号：US20160315065A1

公开(公告)日：2016-10-27

申请号：US15203045

申请日：2016-07-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： CHEN-CHUN CHEN ,  CHIU-JUNG CHEN ,  FU-TSUN TSAI ,  SHIU-KO JANGJIAN ,  CHI-CHERNG JENG ,  HSIN-CHI CHEN

IPC: H01L23/00 ,  H01L27/146 ,  H01L21/027 ,  H01L21/306 ,  H01L21/268

CPC classification number: H01L24/83 ,  H01L21/02019 ,  H01L21/0273 ,  H01L21/268 ,  H01L21/30604 ,  H01L21/76256 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/1469 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/83201 ,  H01L2224/838 ,  H01L2224/83805 ,  H01L2224/8385 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2924/07025

Abstract: A method of manufacturing a semiconductor structure includes providing a first wafer including a surface, removing some portions of the first wafer over the surface to form a plurality of recesses extended over at least a portion of the surface of the first wafer, providing a second wafer, and disposing the second wafer over the surface of the first wafer.

Abstract translation: 制造半导体结构的方法包括提供包括表面的第一晶片，去除表面上的第一晶片的一些部分以形成在第一晶片的表面的至少一部分上延伸的多个凹槽，从而提供第二晶片 并且将第二晶片设置在第一晶片的表面上。

公开(公告)号：US20150206946A1

公开(公告)日：2015-07-23

申请号：US14530320

申请日：2014-10-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： I-CHIH CHEN ,  FU-TSUN TSAI ,  YUNG-FA LEE ,  KO-MIN LIN ,  CHIH-MU HUANG ,  YING-LANG WANG

IPC: H01L29/417 ,  H01L29/45 ,  H01L21/324 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/285

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/76814 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7848

Abstract: A semiconductor device includes a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; and an interconnect plug on the doped region. The raised source/drain region includes a top surface being elevated from a surface of the substrate; and a doped region exposed on the top surface. The doped region includes a dopant concentration greater than any other portions of the raised source/drain region. A bottommost portion of the interconnect plug includes a width approximate to a width of the doped region.

Abstract translation: 半导体器件包括在衬底上的栅极结构; 与栅极结构相邻的凸起的源极/漏极区域; 以及掺杂区域上的互连插头。 升高的源极/漏极区域包括从衬底的表面升高的顶表面; 以及暴露在顶表面上的掺杂区域。 掺杂区域包括大于凸起源极/漏极区域的任何其它部分的掺杂剂浓度。 互连插头的最底部包括近似于掺杂区域的宽度的宽度。

公开(公告)号：US20160111536A1

公开(公告)日：2016-04-21

申请号：US14515225

申请日：2014-10-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： I-CHIH CHEN ,  CHIH-MING HSIEH ,  FU-TSUN TSAI ,  YUNG-FA LEE ,  CHIH-MU HUANG

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/265 ,  H01L21/324 ,  H01L29/7848 ,  H01L29/785

Abstract: Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device including receiving a FinFET precursor including a fin structure formed between isolation regions, and a gate structure formed over a portion of the fin structure such that a sidewall of the fin structure is in contact with a gate spacer of the gate structure; patterning the fin structure to comprise a pattern of at least one upward step rising from the isolation region; forming a capping layer over the fin structure, the isolation region, and the gate structure; performing an annealing process on the FinFET precursor to form at least two dislocations along the upward step; and removing the capping layer.

Abstract translation: 本公开的一些实施例提供一种制造半导体器件的方法，该半导体器件包括接收包括形成在隔离区域之间的鳍结构的FinFET前体，以及形成在鳍结构的一部分上的栅极结构，使得翅片结构的侧壁处于 与栅极结构的栅极间隔物接触; 图案化鳍结构以包括从隔离区域上升的至少一个向上步骤的图案; 在鳍结构，隔离区和栅结构之上形成覆盖层; 对FinFET前体进行退火处理以沿着向上的台阶形成至少两个位错; 并去除覆盖层。

公开(公告)号：US20160005781A1

公开(公告)日：2016-01-07

申请号：US14322469

申请日：2014-07-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： HUAN-EN LIN ,  SHIU-KO JANGJIAN ,  VOLUME CHIEN ,  FU-TSUN TSAI ,  YUNG-LUNG HSU ,  CHI-CHERNG JENG

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14689

Abstract: A backside illuminated (BSI) image sensor device includes: a first substrate including a front side and a back side; a second substrate bonded with the first substrate on the front side; and a blocking layer between the first substrate and the second substrate. The first substrate includes an image sensor, and the image sensor is configured to collect incident light entering from the back side. The second substrate includes a circuit coupled with the image sensor. The blocking layer is configured to block radiation induced by the circuit.

Abstract translation: 背面照明（BSI）图像传感器装置包括：第一基板，包括前侧和后侧; 在前侧与第一基板结合的第二基板; 以及在第一基板和第二基板之间的阻挡层。 第一基板包括图像传感器，并且图像传感器被配置为收集从背面进入的入射光。 第二基板包括与图像传感器耦合的电路。 阻挡层被配置为阻挡由电路引起的辐射。