Imaging device
    1.
    发明授权

    公开(公告)号:US12094894B2

    公开(公告)日:2024-09-17

    申请号:US18350153

    申请日:2023-07-11

    IPC分类号: H01L27/146

    CPC分类号: H01L27/14609

    摘要: An integrated circuit includes a ramp signal generator circuit, a comparator, a counter and a control circuit. The ramp signal generator circuit is configured to generate a ramp reference signal. The comparator configured to compare a pixel output signal and the ramp reference signal thereby generating a comparator output signal. The counter is coupled to the comparator, and configured to be enabled or disabled in response to the comparator output signal. The control circuit coupled to the comparator, and configured to enable or disable the comparator by a first enable signal, the first enable signal generated in response to at least the comparator output signal.

    Pixel circuit, sensing device, and method thereof

    公开(公告)号:US11289529B2

    公开(公告)日:2022-03-29

    申请号:US16837912

    申请日:2020-04-01

    摘要: A pixel circuit includes: a photodiode capable of generating electrical current according to an incoming light signal; a control circuit coupled to the photodiode for selectively coupling a cathode of the photodiode to a first reference voltage to generate the electrical current according to a first control signal; and an output circuit coupled to the control circuit for selectively coupling a second reference voltage to a connecting terminal between the control circuit and the output circuit and to generate an output signal according to a reset signal and a select signal.

    Semiconductor device with low random telegraph signal noise

    公开(公告)号:US11569346B2

    公开(公告)日:2023-01-31

    申请号:US17378505

    申请日:2021-07-16

    摘要: A semiconductor device includes a source/drain diffusion area, a first doped region and a gate. The source/drain diffusion area, defined between a first isolation structure and a second isolation structure, includes a source region, a drain region and a device channel. The first doped region, disposed along a first junction between the device channel and the first isolation structure, is separated from at least one of the source region and the drain region. The first doped region has a dopant concentration higher than that of the device channel. The gate is disposed over the source/drain diffusion area. The first doped region is located within a projected area of the gate onto the source/drain diffusion area, the first isolation structure and the second isolation structure. A length of the first doped region is shorter than a length of the gate in a direction from the source region to the drain region.

    Imaging device
    5.
    发明授权

    公开(公告)号:US11705466B2

    公开(公告)日:2023-07-18

    申请号:US17098963

    申请日:2020-11-16

    IPC分类号: H01L27/146

    CPC分类号: H01L27/14609

    摘要: An integrated circuit includes a comparator, a counter and a control circuit. The comparator is configured to generate a comparator output signal in response to a pixel output signal and a reference signal. The counter is coupled to the comparator, and configured to be enabled or disabled in response to the comparator output signal. The control circuit is coupled to the comparator, and configured to enable or disable the comparator by a first enable signal. The first enable signal is generated in response to at least the comparator output signal.

    HIGH-SPEED READOUT IMAGE SENSOR
    9.
    发明公开

    公开(公告)号:US20240014245A1

    公开(公告)日:2024-01-11

    申请号:US18149746

    申请日:2023-01-04

    IPC分类号: H01L27/146

    CPC分类号: H01L27/14636 H01L27/14634

    摘要: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a first chip bonded to a second chip. The first chip includes a semiconductor substrate. The first chip includes a first transistor cell and a second transistor cell. The second transistor cell is laterally spaced from the first transistor cell. A first through-substrate via (TSV) extends vertically through the semiconductor substrate. The first transistor cell is electrically coupled to the first TSV. A second TSV extends vertically through the first semiconductor substrate. The second transistor cell is electrically coupled to the second TSV. The second chip comprises a first readout circuit that is electrically coupled to the first TSV and the second TSV. The first readout circuit is disposed laterally between the first TSV and the second TSV. The first readout circuit is configured to receive a first signal from the first transistor cell.