公开(公告)号：US10439561B2

公开(公告)日：2019-10-08

申请号：US15891791

申请日：2018-02-08

Applicant: Texas Instruments Incorporated

Inventor： Adam Lee Shook

IPC: H03F1/02 ,  H03F1/26 ,  H03F1/30 ,  H03F3/38 ,  H03F3/393 ,  H03F3/45

Abstract: An output of a first amplifier is coupled to an input of a first track and hold circuit and an input of a second track and hold circuit. An input of a first summing circuit is also coupled to an output of the first track and hold circuit and an output of the second track and hold circuit. In addition, an input of a second summing circuit is coupled to the output of the first track and hold circuit and the output of the second track and hold circuit. Moreover, an input of a third summing circuit coupled to an output of a modulator and an output of the second summing circuit, and an output of the third summing circuit coupled to an input of the first amplifier.

公开(公告)号：US09294000B1

公开(公告)日：2016-03-22

申请号：US14484892

申请日：2014-09-12

Applicant: Texas Instruments Incorporated

Inventor： Adam Lee Shook

IPC: H02M3/337 ,  H02M3/335

CPC classification number: H02M3/158 ,  H02M7/48 ,  H02M7/5387 ,  H03F3/04

Abstract: A circuit and method for providing a fully integrated differential boost converter and amplifier. A first half bridge circuit has a first output node and a first switching node. A second half bridge circuit has a second output node and a second switching node. A capacitive load is coupled between the first output node and the second output node. An inductor is coupled between the first switching node and the second switching node. Control modes are provided to couple the first output node to a supply voltage and the first switching node to ground; to couple the first output node to the supply voltage and the second switching node to ground; to couple the second output node to the supply voltage and the first switching node to ground; and to couple the second output node to the supply voltage and the second switching node to ground.

Abstract translation: 一种用于提供完全集成的差分升压转换器和放大器的电路和方法。 第一半桥电路具有第一输出节点和第一交换节点。 第二半桥电路具有第二输出节点和第二交换节点。 电容性负载耦合在第一输出节点和第二输出节点之间。 电感器耦合在第一交换节点和第二交换节点之间。 提供控制模式以将第一输出节点耦合到电源电压，并将第一交换节点耦合到地; 将第一输出节点耦合到电源电压，将第二开关节点耦合到地; 将第二输出节点耦合到电源电压，将第一交换节点耦合到地; 并将第二输出节点耦合到电源电压，将第二开关节点耦合到地。

公开(公告)号：US11108389B2

公开(公告)日：2021-08-31

申请号：US17020608

申请日：2020-09-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xiong Li ,  Adam Lee Shook

IPC: H03K17/567 ,  B60R16/033 ,  H03K17/687 ,  H03K17/60 ,  H03K17/74

Abstract: In a gate driver, a comparator input is adapted to be coupled through a resistor and a diode to a first transistor. A latch input is coupled to a comparator output. A second transistor has a first control terminal and a first output terminal. The first output terminal is adapted to be coupled to a control terminal of the first transistor. A third transistor is smaller than the second transistor. The third transistor has a second control terminal and a second output terminal. The second output terminal is adapted to be coupled to the control terminal of the first transistor. Control logic has a logic input and first and second logic outputs. The logic input is coupled to a latch output. The first logic output is coupled to the first control terminal. The second logic output is coupled to the second control terminal.

公开(公告)号：US10784857B1

公开(公告)日：2020-09-22

申请号：US16428455

申请日：2019-05-31

Applicant: Texas Instruments Incorporated

Inventor： Xiong Li ,  Adam Lee Shook

IPC: H03K17/567 ,  B60R16/033 ,  H03K17/687 ,  H03K17/60 ,  H03K17/74

Abstract: Adaptive gate drivers and related methods and systems are disclosed. An example gate driver system includes a comparator, a latch having first and second inputs and outputs, the first input coupled to the comparator, a timer having an input and an output, the input coupled to the first output of the latch, the output coupled to the second input of the latch, control logic having an input and first and second outputs, the input coupled to the second output of the latch, first and second transistors having a gate, a first buffer having an input and an output, the input coupled to the first output of the control logic, the output coupled to the gate of the first transistor, and a second buffer having an input and an output, the input coupled to the second output of the control logic, the output coupled to the gate of the second transistor.

公开(公告)号：US20180254752A1

公开(公告)日：2018-09-06

申请号：US15891791

申请日：2018-02-08

Applicant: Texas Instruments Incorporated

Inventor： Adam Lee Shook

IPC: H03F1/26 ,  H03F3/38 ,  H03F1/30

CPC classification number: H03F1/26 ,  H03F1/30 ,  H03F1/303 ,  H03F3/38 ,  H03F3/393 ,  H03F3/45183 ,  H03F3/45775 ,  H03F2200/375 ,  H03F2203/45212

Abstract: An output of a first amplifier is coupled to an input of a first track and hold circuit and an input of a second track and hold circuit. An input of a first summing circuit is also coupled to an output of the first track and hold circuit and an output of the second track and hold circuit. In addition, an input of a second summing circuit is coupled to the output of the first track and hold circuit and the output of the second track and hold circuit. Moreover, an input of a third summing circuit coupled to an output of a modulator and an output of the second summing circuit, and an output of the third summing circuit coupled to an input of the first amplifier.

公开(公告)号：US20160079860A1

公开(公告)日：2016-03-17

申请号：US14484892

申请日：2014-09-12

Applicant: Texas Instruments Incorporated

Inventor： Adam Lee Shook

IPC: H02M3/337 ,  H02M3/335

CPC classification number: H02M3/158 ,  H02M7/48 ,  H02M7/5387 ,  H03F3/04

Abstract: A circuit and method for providing a fully integrated differential boost converter and amplifier. A first half bridge circuit has a first output node and a first switching node. A second half bridge circuit has a second output node and a second switching node. A capacitive load is coupled between the first output node and the second output node. An inductor is coupled between the first switching node and the second switching node. Control modes are provided to couple the first output node to a supply voltage and the first switching node to ground; to couple the first output node to the supply voltage and the second switching node to ground; to couple the second output node to the supply voltage and the first switching node to ground; and to couple the second output node to the supply voltage and the second switching node to ground.

Abstract translation: 一种用于提供完全集成的差分升压转换器和放大器的电路和方法。 第一半桥电路具有第一输出节点和第一交换节点。 第二半桥电路具有第二输出节点和第二交换节点。 电容性负载耦合在第一输出节点和第二输出节点之间。 电感器耦合在第一交换节点和第二交换节点之间。 提供控制模式以将第一输出节点耦合到电源电压，并将第一交换节点耦合到地; 将第一输出节点耦合到电源电压，将第二开关节点耦合到地; 将第二输出节点耦合到电源电压，将第一交换节点耦合到地; 并将第二输出节点耦合到电源电压，将第二开关节点耦合到地。

公开(公告)号：US11082052B2

公开(公告)日：2021-08-03

申请号：US16854584

申请日：2020-04-21

Applicant: Texas Instruments Incorporated

Inventor： Byungchul Jang ,  Adam Lee Shook ,  Pankaj Pandey

IPC: G06F1/04 ,  G06F3/041 ,  H03K3/00 ,  H03K3/012 ,  H03L7/099 ,  G05F1/59 ,  G05F1/575 ,  H03K17/687 ,  H03K17/567

Abstract: Frequency lock loop (FLL) circuits, low voltage dropout regulator circuits, and related methods are disclosed. An example gate driver integrated circuit includes a first die including a FLL circuit to generate a first clock signal having a first phase and a first frequency, a second clock signal having the first frequency and a second phase different from the first phase, and control a plurality of switching networks to increase the first frequency to a second frequency, and generate a feedback voltage based on the second frequency, and a second die coupled to the first die, the second die including a low dropout (LDO) circuit and a driver, the driver configured to control a transistor based on the first frequency, the second die configured to be coupled to the transistor, the LDO circuit to generate a pass-gate voltage based on an output current of the LDO circuit satisfying a current threshold.

公开(公告)号：US20210111726A1

公开(公告)日：2021-04-15

申请号：US16854584

申请日：2020-04-21

Applicant: Texas Instruments Incorporated

Inventor： Byungchul Jang ,  Adam Lee Shook ,  Pankaj Pandey

IPC: H03L7/099 ,  G05F1/59 ,  H03K17/567 ,  H03K17/687 ,  G05F1/575

Abstract: Frequency lock loop (FLL) circuits, low voltage dropout regulator circuits, and related methods are disclosed. An example gate driver integrated circuit includes a first die including a FLL circuit to generate a first clock signal having a first phase and a first frequency, a second clock signal having the first frequency and a second phase different from the first phase, and control a plurality of switching networks to increase the first frequency to a second frequency, and generate a feedback voltage based on the second frequency, and a second die coupled to the first die, the second die including a low dropout (LDO) circuit and a driver, the driver configured to control a transistor based on the first frequency, the second die configured to be coupled to the transistor, the LDO circuit to generate a pass-gate voltage based on an output current of the LDO circuit satisfying a current threshold.

公开(公告)号：US10483977B1

公开(公告)日：2019-11-19

申请号：US16275401

申请日：2019-02-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey Wallace Berwick ,  Adam Lee Shook ,  Munaf Hussain Shaik ,  Mohit Chawla

IPC: H03K19/0185 ,  H03K19/0175

Abstract: A level shifter circuit includes a high voltage latch circuit, a low voltage latch circuit, a high state pulse generator, and a low state pulse generator. The high voltage latch circuit includes a non-inverting output terminal, an inverting output terminal, a high state trigger input terminal, and a low state trigger input terminal. The low voltage latch circuit includes a high state trigger input terminal and a low state trigger input terminal. The high state trigger input terminal is coupled to the inverting output terminal of the high voltage latch circuit. The low state trigger input terminal is coupled to the non-inverting output terminal of the high voltage latch circuit. The high state pulse generator is coupled to the high state trigger input terminal of the high voltage latch circuit. The low state pulse generator is coupled to the low state trigger input terminal of the high voltage latch circuit.