公开(公告)号：US20230326002A1

公开(公告)日：2023-10-12

申请号：US18333151

申请日：2023-06-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra MODY, JR. ,  Veeramanikandan RAJU ,  Niraj NANDAN ,  Samuel Paul VISALLI ,  Jason A.T. JONES ,  Kedar Satish CHITNIS ,  Gregory Raymond SHURTZ ,  Prithvi Shankar YEYYADI ANANTHA ,  Sriramakrishnan GOVINDARAJAN

IPC: G06T7/00 ,  G06T1/20 ,  G06T3/40 ,  G05B23/02

CPC classification number: G06T7/0002 ,  G06T1/20 ,  G06T3/40 ,  H04N17/00 ,  G06T7/97 ,  G06T2207/10016 ,  G05B23/0259

Abstract: Systems, methods and devices that improve fault detection capability of an imaging/vision hardware accelerator are provided. One such system includes a hardware accelerator, a signature generator, a signature processor, and a controller. These components cooperate to generate first and second output frames based on first and second reference frames, respectively; generate a third output frame based on a use-case frame; generate first and second image signatures based on the first and second output frames, respectively; compare the first image signature to a stored first reference image signature and output a first result; and compare the second image signature to a stored second reference image signature and output a second result. The controller determines, based on the results, whether the hardware accelerator has a fault at either a first time or a second time. When no fault is detected at either time, the controller analyzes the use-case frame for designation as an adaptive reference frame.

公开(公告)号：US20200210256A1

公开(公告)日：2020-07-02

申请号：US16377404

申请日：2019-04-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kedar Satish CHITNIS ,  Charles Lance FUOCO ,  Sriramakrishnan GOVINDARAJAN ,  Mihir Narendra MODY ,  William A. MILLS ,  Gregory Raymond SHURTZ ,  Amritpal Singh MUNDRA

IPC: G06F9/54 ,  G06F9/50 ,  G06F9/38 ,  G06F9/48 ,  G06F9/455

Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.

公开(公告)号：US20240296220A1

公开(公告)日：2024-09-05

申请号：US18662227

申请日：2024-05-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kedar Satish CHITNIS ,  Mihir Narendra MODY ,  Amritpal Singh MUNDRA ,  Yashwant DUTT ,  Gregory Raymond SHURTZ ,  Robert John TIVY

IPC: G06F21/54 ,  G06F9/48 ,  G06F21/55 ,  G06F21/79

CPC classification number: G06F21/54 ,  G06F9/485 ,  G06F21/554 ,  G06F21/79

Abstract: Devices, systems and techniques for implementing freedom from interference (FFI) access rules. In an example, a device includes a set of primary components, a set of secondary components, and an interconnected coupled between the two sets of components. Each primary component of the set of primary components has an access identifier, among multiple access attributes, and an access attribute, among multiple access modes. Each secondary component of the set of secondary components is protected by a firewall. Each firewall is configured to specify, for each specific combination of an access identifier and access attribute, whether access to the associated secondary component is permitted and what type of access is permitted.

公开(公告)号：US20230185904A1

公开(公告)日：2023-06-15

申请号：US17550948

申请日：2021-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kedar Satish CHITNIS ,  Mihir Narendra MODY ,  Amritpal Singh MUNDRA ,  Yashwant DUTT ,  Gregory Raymond SHURTZ ,  Robert John TIVY

IPC: G06F21/54 ,  G06F21/55 ,  G06F21/79 ,  G06F9/48

CPC classification number: G06F21/54 ,  G06F9/485 ,  G06F21/79 ,  G06F21/554

Abstract: A method of enabling memory access freedom from interference (FFI) rules, comprising: determining a first safety privilege access ID (PrivID) for a first component of a system (e.g., based on Automotive Safety Integrity Level (ASIL) attributes of tasks executed by the first component); determining a first access attribute for a first software task executing on the first component; receiving, at a first firewall component of the system, a request from the first software task to access a first memory region of a second component of the system, wherein the request specifies the first PrivID and the first access attribute; and determining, by the first firewall component, whether to permit the first software task to access the first memory region based on the first PrivID, the first access attribute, and the first memory region.

公开(公告)号：US20240427717A1

公开(公告)日：2024-12-26

申请号：US18819007

申请日：2024-08-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra MODY ,  Ankur ANKUR ,  Vivek Vilas DHANDE ,  Kedar Satish CHITNIS ,  Niraj NANDAN ,  Brijesh JADAV ,  Shyam JAGANNATHAN ,  Prithvi Shankar YEYYADI ANANTHA ,  Santhanakrishnan Narayanan NARAYANAN

IPC: G06F13/28 ,  G06F9/48 ,  G06F13/16 ,  G06F13/42 ,  G06F15/78

Abstract: Systems and methods in which trace data is efficiently managed are provided. An example system includes a memory, a first interface, and a processing resource communicably coupled to the first interface and to the memory. The processing resource includes a buffer, and a first controller to transmit a set of data from the buffer with associated trace information for the set of data to the memory. A second controller transmits the set of data with the associated trace information from the memory to a second interface.

公开(公告)号：US20240320045A1

公开(公告)日：2024-09-26

申请号：US18675294

申请日：2024-05-28

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra MODY ,  Kedar Satish CHITNIS ,  Kumar DESAPPAN ,  David SMITH ,  Pramod Kumar SWAMI ,  Shyam JAGANNATHAN

IPC: G06F9/50 ,  G06F9/455 ,  G06F12/00 ,  G06F12/02 ,  G06N3/02 ,  G06N3/10 ,  G06N20/00

CPC classification number: G06F9/5016 ,  G06F9/5077 ,  G06F12/00 ,  G06F12/0223 ,  G06F2009/45583 ,  G06F9/50 ,  G06F9/5022 ,  G06N3/02 ,  G06N3/10 ,  G06N20/00

Abstract: Techniques for executing machine learning (ML) models including receiving an indication to run an ML model on a processing core; receiving a static memory allocation for running the ML model on the processing core; determining that a layer of the ML model uses more memory than the static memory allocated; transmitting, to a shared memory, a memory request for blocks of the shared memory; receiving an allocation of the requested blocks; running the layer of the ML model using the static memory and the range of memory addresses; and outputting results of running the layer of the ML model.

公开(公告)号：US20230267084A1

公开(公告)日：2023-08-24

申请号：US17677638

申请日：2022-02-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra MODY, JR. ,  Ankur ANKUR ,  Vivek Vilas DHANDE ,  Kedar Satish CHITNIS ,  Niraj NANDAN ,  Brijesh JADAV ,  Shyam JAGANNATHAN ,  Prithvi Shankar YEYYADI ANANTHA ,  Santhanakrishnan Narayanan NARAYANAN

IPC: G06F13/28 ,  G06F13/16 ,  G06F13/42 ,  G06F15/78 ,  G06F9/48

CPC classification number: G06F13/28 ,  G06F13/1673 ,  G06F13/4221 ,  G06F15/7807 ,  G06F9/4881

Abstract: A system-on-chip (SoC) in which trace data is managed includes a first memory device, a first interface to couple the first memory to a second memory external to the system-on-chip, and a first processing resource coupled to the first interface and the first memory device. The first processing resource includes a data buffer and a first direct access memory (DMA) controller. The first DMA controller transmits data from the data buffer to the first interface over a first channel, and transmits the data from the data buffer with associated trace information for the data to the first memory device over a second channel.

公开(公告)号：US20230013998A1

公开(公告)日：2023-01-19

申请号：US17378841

申请日：2021-07-19

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra MODY ,  Kedar Satish CHITNIS ,  Kumar DESAPPAN ,  David SMITH ,  Pramod Kumar SWAMI ,  Shyam JAGANNATHAN

IPC: G06F9/50 ,  G06N20/00

Abstract: Techniques for executing machine learning (ML) models including receiving an indication to run an ML model on a processing core; receiving a static memory allocation for running the ML model on the processing core; determining that a layer of the ML model uses more memory than the static memory allocated; transmitting, to a shared memory, a memory request for blocks of the shared memory; receiving an allocation of the requested blocks; running the layer of the ML model using the static memory and the range of memory addresses; and outputting results of running the layer of the ML model.

公开(公告)号：US20220391776A1

公开(公告)日：2022-12-08

申请号：US17342037

申请日：2021-06-08

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra MODY ,  Kumar DESAPPAN ,  Kedar Satish CHITNIS ,  Pramod Kumar SWAMI ,  Kevin Patrick LAVERY ,  Prithvi Shankar YEYYADI ANANTHA ,  Shyam JAGANNATHAN

IPC: G06N20/20 ,  G06F9/52 ,  G06F9/455

Abstract: Techniques for executing machine learning (ML) models including receiving an indication to run a ML model, receiving synchronization information for organizing the running of the ML model with other ML models, determining, based on the synchronization information, to delay running the ML model, delaying the running of the ML model, determining, based on the synchronization information, a time to run the ML model; and running the ML model at the time.