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    Droop reduction circuit for charge pump buck converter
    4.
    发明授权
    Droop reduction circuit for charge pump buck converter 有权
    电荷泵降压转换器的下降电路

    公开(公告)号：US09413232B2

    公开(公告)日：2016-08-09

    申请号：US14734720

    申请日：2015-06-09

    Applicant: Texas Instruments Incorporated

    Inventor： Erick Omar Torres ,  Byungchul Jang

    IPC: H02M3/07 ,  H02M3/158 ,  H02M3/16 ,  H02M3/156 ,  H02M3/28 ,  H02M1/00

    CPC classification number: H02M3/07 ,  H02M3/156 ,  H02M3/1582 ,  H02M3/16 ,  H02M3/285 ,  H02M2001/009

    Abstract: A Charge Pump Buck Converter (CPBC) includes a BC including an inductor and a CP coupled in parallel. Control logic is coupled to a switch driver coupled to a power switch(es). Control circuitry includes a voltage sensor sensing Vout and a voltage level generator for generating a first voltage level coupled to the CP stage and a second voltage level coupled to a duty cycle/rate generator block providing an input to an under voltage (UV) monitor coupled between OUT and the control logic. The control circuitry disables the CP when Vout>a first Vout level and controls the BC to regulate to a second Vout level>the first Vout level. During handoff between CP and BC during power up if Vout drops below a UV threshold, the UV monitor block modifies an input applied to the control logic for increasing charging supplied to the inductor.

    Abstract translation: 电荷泵降压转换器（CPBC）包括一个BC，它包括并联耦合的电感和CP。 控制逻辑耦合到耦合到电源开关的开关驱动器。 控制电路包括感测Vout的电压传感器和用于产生耦合到CP级的第一电压电平的电压传感器以及耦合到占空比/速率发生器模块的第二电压电平，该负载电平发生器模块向欠耦合 在OUT和控制逻辑之间。 当Vout>第一Vout电平时，控制电路禁用CP，并且控制BC调节到第一Vout电平>第一Vout电平。 如果Vout下降到UV阈值以下，在上电期间CP和BC之间的切换期间，UV监视器块修改施加到控制逻辑的输入，以增加提供给电感器的充电。

    Low-loss step-up and step-down voltage converter
    5.
    发明授权
    Low-loss step-up and step-down voltage converter 有权
    低损耗升压和降压变压器

    公开(公告)号：US09385600B2

    公开(公告)日：2016-07-05

    申请号：US14088012

    申请日：2013-11-22

    Applicant: Texas Instruments Incorporated

    Inventor： Erick Omar Torres ,  Harish Venkataraman ,  Byungchul Jang

    IPC: H02M3/158 ,  H02M3/07 ,  H02M1/00

    CPC classification number: H02M3/158 ,  H02M3/07 ,  H02M3/1582 ,  H02M3/1584 ,  H02M2001/0048 ,  Y02B70/1491

    Abstract: A switch-mode DC-DC voltage converter including a boost stage in the form of a charge pump and a buck stage. Control circuitry is provided that enables the operation of the buck stage while the charge pump stage is also enabled, followed by disabling of the charge pump stage as the input voltage and output voltage increase. The buck converter stage is constructed so that it regulates the output voltage at a voltage above that which disables the charge pump stage. Conduction losses in the main current path, due to the necessity of a power FET or other switching device, are avoided.

    Abstract translation: 一种开关模式的DC-DC电压转换器，包括电荷泵和降压级形式的升压级。 提供了控制电路，其能够在电荷泵级被使能的同时进行降压级的操作，随后当输入电压和输出电压增加时禁止电荷泵级。 降压转换器级被构造成使得其在高于使电荷泵级无效的电压下调节输出电压。 避免了由于功率FET或其他开关器件的需要导致的主电流通路中的导通损耗。

    Frequency lock loop circuits, low voltage dropout regulator circuits, and related methods
    6.
    发明授权
    Frequency lock loop circuits, low voltage dropout regulator circuits, and related methods 有权

    公开(公告)号：US11082052B2

    公开(公告)日：2021-08-03

    申请号：US16854584

    申请日：2020-04-21

    Applicant: Texas Instruments Incorporated

    Inventor： Byungchul Jang ,  Adam Lee Shook ,  Pankaj Pandey

    IPC: G06F1/04 ,  G06F3/041 ,  H03K3/00 ,  H03K3/012 ,  H03L7/099 ,  G05F1/59 ,  G05F1/575 ,  H03K17/687 ,  H03K17/567

    Abstract: Frequency lock loop (FLL) circuits, low voltage dropout regulator circuits, and related methods are disclosed. An example gate driver integrated circuit includes a first die including a FLL circuit to generate a first clock signal having a first phase and a first frequency, a second clock signal having the first frequency and a second phase different from the first phase, and control a plurality of switching networks to increase the first frequency to a second frequency, and generate a feedback voltage based on the second frequency, and a second die coupled to the first die, the second die including a low dropout (LDO) circuit and a driver, the driver configured to control a transistor based on the first frequency, the second die configured to be coupled to the transistor, the LDO circuit to generate a pass-gate voltage based on an output current of the LDO circuit satisfying a current threshold.

    FREQUENCY LOCK LOOP CIRCUITS, LOW VOLTAGE DROPOUT REGULATOR CIRCUITS, AND RELATED METHODS
    7.
    发明申请
    FREQUENCY LOCK LOOP CIRCUITS, LOW VOLTAGE DROPOUT REGULATOR CIRCUITS, AND RELATED METHODS 有权

    公开(公告)号：US20210111726A1

    公开(公告)日：2021-04-15

    申请号：US16854584

    申请日：2020-04-21

    Applicant: Texas Instruments Incorporated

    Inventor： Byungchul Jang ,  Adam Lee Shook ,  Pankaj Pandey

    IPC: H03L7/099 ,  G05F1/59 ,  H03K17/567 ,  H03K17/687 ,  G05F1/575

    Abstract: Frequency lock loop (FLL) circuits, low voltage dropout regulator circuits, and related methods are disclosed. An example gate driver integrated circuit includes a first die including a FLL circuit to generate a first clock signal having a first phase and a first frequency, a second clock signal having the first frequency and a second phase different from the first phase, and control a plurality of switching networks to increase the first frequency to a second frequency, and generate a feedback voltage based on the second frequency, and a second die coupled to the first die, the second die including a low dropout (LDO) circuit and a driver, the driver configured to control a transistor based on the first frequency, the second die configured to be coupled to the transistor, the LDO circuit to generate a pass-gate voltage based on an output current of the LDO circuit satisfying a current threshold.

    LOW-LOSS STEP-UP AND STEP-DOWN VOLTAGE CONVERTER
    8.
    发明申请
    LOW-LOSS STEP-UP AND STEP-DOWN VOLTAGE CONVERTER 有权
    低损耗升压和降压电压转换器

    公开(公告)号：US20150145497A1

    公开(公告)日：2015-05-28

    申请号：US14088012

    申请日：2013-11-22

    Applicant: Texas Instruments Incorporated

    Inventor： Erick Omar Torres ,  Harish Venkataraman ,  Byungchul Jang

    IPC: H02M3/158 ,  H02M3/157

    CPC classification number: H02M3/158 ,  H02M3/07 ,  H02M3/1582 ,  H02M3/1584 ,  H02M2001/0048 ,  Y02B70/1491

    Abstract: A switch-mode DC-DC voltage converter including a boost stage in the form of a charge pump and a buck stage. Control circuitry is provided that enables the operation of the buck stage while the charge pump stage is also enabled, followed by disabling of the charge pump stage as the input voltage and output voltage increase. The buck converter stage is constructed so that it regulates the output voltage at a voltage above that which disables the charge pump stage. Conduction losses in the main current path, due to the necessity of a power FET or other switching device, are avoided.

    Abstract translation: 一种开关模式的DC-DC电压转换器，包括电荷泵和降压级形式的升压级。 提供了控制电路，其能够在电荷泵级被使能的同时进行降压级的运行，随后当输入电压和输出电压增加时禁止电荷泵级。 降压转换器级被构造成使得其在高于使电荷泵级无效的电压下调节输出电压。 避免了由于功率FET或其他开关器件的需要导致的主电流通路中的导通损耗。

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