公开(公告)号：US09154133B2

公开(公告)日：2015-10-06

申请号：US13630721

申请日：2012-09-28

Applicant: Texas Instruments Incorporated

Inventor： Muhammad Yusuf Ali ,  Rajkumar Sankaralingam ,  Charles M. Branch

IPC: H03H9/46 ,  H03K19/003 ,  H02H9/04 ,  H01L27/02

CPC classification number: H03K19/00384 ,  H01L27/0266 ,  H02H9/046

Abstract: An inverter type level shifter includes a first power supply voltage and a first ground voltage. A first inverter operates on the first power supply voltage and the first ground voltage to generate a first inverter output. The first inverter includes a first PMOS transistor having a drain coupled to a source of a blocking PMOS transistor and a first NMOS transistor having a drain coupled to a source of a blocking NMOS transistor. The level shifter further includes a second power supply voltage and a second ground voltage, and a second inverter coupled to the first inverter output and operates on the second power supply voltage and the second ground voltage. The blocking PMOS provides the required blocking on the event of the voltage spike in the second power supply voltage w.r.t the first power supply voltage and the blocking NMOS transistor provides the required blocking on the event of the voltage spike in the second ground voltage with respect to the first ground voltage.

Abstract translation: 逆变器型电平移位器包括第一电源电压和第一接地电压。 第一逆变器对第一电源电压和第一接地电压进行操作以产生第一逆变器输出。 第一反相器包括第一PMOS晶体管，其具有耦合到阻塞PMOS晶体管的源极的漏极和具有耦合到阻塞NMOS晶体管的源极的漏极的第一NMOS晶体管。 电平移位器还包括第二电源电压和第二接地电压，以及第二反相器，耦合到第一反相器输出并对第二电源电压和第二接地电压进行操作。 阻塞PMOS在第一电源电压的第二电源电压中的电压尖峰的事件上提供所需的阻塞，并且阻塞NMOS晶体管相对于第二电源电压在第二接地电压中的电压尖峰的事件上提供所需的阻塞 第一接地电压。

公开(公告)号：US11916062B2

公开(公告)日：2024-02-27

申请号：US16724129

申请日：2019-12-20

Applicant: Texas Instruments Incorporated

Inventor： Xianzhi Dai ,  Rajkumar Sankaralingam

IPC: H02H9/04 ,  H01L27/02 ,  H02H3/20

CPC classification number: H01L27/0266 ,  H02H3/20 ,  H02H9/04 ,  H02H9/041 ,  H01L27/0285

Abstract: A microelectronic device has a protected line and a reference line, and an active field effect transistor (FET) coupled between the protected line and the reference line. The microelectronic device includes an electrostatic discharge (ESD) trigger circuit coupled to the gate of the active FET, to turn on the active FET when an ESD event occurs on the protected line. The microelectronic device further includes a transient detection circuit having a high bandwidth detector, an ESD detector, and an output driver. The ESD detector is configured to provide a CLEAR signal to the output driver when an ESD event occurs on the protected line. The output driver is configured to turn off the active FET when a voltage surge, which can damage the active FET, occurs on the protected line, but enable operation of the active FET by the ESD trigger circuit during an ESD event.

公开(公告)号：US09425188B2

公开(公告)日：2016-08-23

申请号：US14494316

申请日：2014-09-23

Applicant: Texas Instruments Incorporated

Inventor： Muhammad Yusuf Ali ,  Rajkumar Sankaralingam

IPC: H02H1/00 ,  H02H1/04 ,  H02H3/22 ,  H02H9/04 ,  H01L27/02

CPC classification number: H01L27/0285

Abstract: An electrostatic discharge (ESD) protection integrated circuit (IC) includes a substrate having a semiconductor surface, a high power supply rail (VDD) and a low power supply rail (VSS) on the semiconductor surface. A trigger circuit including at least one trigger input and at least one trigger output is coupled between VDD and VSS. An active shunt including at least a large MOSFET is coupled between VDD and VSS. The trigger output is coupled to a gate electrode of the large MOSFET, and at least one diode or diode connected transistor (blocking diode) is coupled between VDD and the trigger circuit, within the trigger circuit or between the trigger output and gate electrode.

Abstract translation: 静电放电（ESD）保护集成电路（IC）包括在半导体表面上具有半导体表面的衬底，高电源轨（VDD）和低电源轨（VSS）。 包括至少一个触发输入和至少一个触发输出的触发电路耦合在VDD和VSS之间。 在VDD和VSS之间耦合至少包括一个大型MOSFET的有源分流器。 触发输出耦合到大型MOSFET的栅电极，并且至少一个二极管或二极管连接的晶体管（阻塞二极管）耦合在VDD和触发电路之间，触发电路内或触发输出与栅电极之间。

公开(公告)号：US12027612B2

公开(公告)日：2024-07-02

申请号：US17340255

申请日：2021-06-07

Applicant: Texas Instruments Incorporated

Inventor： Karmel Kranthi Nagothu ,  James Paul Di Sarro ,  Rajkumar Sankaralingam

IPC: H01L29/08 ,  H01L27/02 ,  H01L29/74

CPC classification number: H01L29/74 ,  H01L27/0262 ,  H01L29/0834 ,  H01L29/0839

Abstract: A lateral semiconductor controlled rectifier (SCR) includes a pwell and an nwell A plurality of p+ contact regions connect to the pwell and are spaced apart from one another by a dielectric material along a width of the pwell. There are a plurality of n+ contact regions connect to the nwell and are spaced apart from one another by dielectric material along a width of the nwell.

公开(公告)号：US20170229447A1

公开(公告)日：2017-08-10

申请号：US15015435

申请日：2016-02-04

Applicant: Texas Instruments Incorporated

Inventor： Rajkumar Sankaralingam ,  Aravind Appaswamy

IPC: H01L27/02

CPC classification number: H01L27/0251 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0266 ,  H01L27/0285

Abstract: An integrated circuit with a boot strap clamp protecting an input/output transistor coupled to a bondpad where the boot strap clamp is comprised of a protection resistor coupled between the input/output transistor and the bondpad and a bootstrap clamp transistor coupled between the drain of the input/output transistor and the gate of the input/output transistor. An integrated circuit with a boot strap clamp protecting an input/output transistor coupled to a bondpad where the boot strap clamp is comprised of a protection resistor coupled between the input/output transistor and the bondpad and a bootstrap clamp diode coupled between the drain of the input/output transistor and the gate of the input/output transistor and a biasing resistor coupled between the gate and source of the input/output transistor.

公开(公告)号：US20220223723A1

公开(公告)日：2022-07-14

申请号：US17340255

申请日：2021-06-07

Applicant: Texas Instruments Incorporated

Inventor： Karmel Kranthi Nagothu ,  James Paul Di Sarro ,  Rajkumar Sankaralingam

IPC: H01L29/74 ,  H01L27/02 ,  H01L29/08

Abstract: A lateral semiconductor controlled rectifier (SCR) includes a pwell and an nwell A plurality of p+ contact regions connect to the pwell and are spaced apart from one another by a dielectric material along a width of the pwell. There are a plurality of n+ contact regions connect to the nwell and are spaced apart from one another by dielectric material along a width of the nwell.

公开(公告)号：US09741705B1

公开(公告)日：2017-08-22

申请号：US15015435

申请日：2016-02-04

Applicant: Texas Instruments Incorporated

Inventor： Rajkumar Sankaralingam ,  Aravind Appaswamy

IPC: H01L27/02

CPC classification number: H01L27/0251 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0266 ,  H01L27/0285

Abstract: An integrated circuit with a boot strap clamp protecting an input/output transistor coupled to a bondpad where the boot strap clamp is comprised of a protection resistor coupled between the input/output transistor and the bondpad and a bootstrap clamp transistor coupled between the drain of the input/output transistor and the gate of the input/output transistor. An integrated circuit with a boot strap clamp protecting an input/output transistor coupled to a bondpad where the boot strap clamp is comprised of a protection resistor coupled between the input/output transistor and the bondpad and a bootstrap clamp diode coupled between the drain of the input/output transistor and the gate of the input/output transistor and a biasing resistor coupled between the gate and source of the input/output transistor.

公开(公告)号：US11527530B2

公开(公告)日：2022-12-13

申请号：US17321492

申请日：2021-05-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Krishna Praveen Mysore Rajagopal ,  James Paul DiSarro ,  Ann Margaret Concannon ,  Rajkumar Sankaralingam

IPC: H01L27/02 ,  H02H9/04

Abstract: An ESD protection system including structure to operate an IC during nominal conditions, to protect the IC during an ESD event, and to allow the IC to operate during slow rising input node voltages that exceed nominal conditions.

公开(公告)号：US20220223581A1

公开(公告)日：2022-07-14

申请号：US17321492

申请日：2021-05-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Krishna Praveen Mysore Rajagopal ,  James Paul DiSarro ,  Ann Margaret Concannon ,  Rajkumar Sankaralingam

IPC: H01L27/02 ,  H02H9/04

Abstract: An ESD protection system including structure to operate an IC during nominal conditions, to protect the IC during an ESD event, and to allow the IC to operate during slow rising input node voltages that exceed nominal conditions.

公开(公告)号：US20200321331A1

公开(公告)日：2020-10-08

申请号：US16724129

申请日：2019-12-20

Applicant: Texas Instruments Incorporated

Inventor： Xianzhi Dai ,  Rajkumar Sankaralingam

IPC: H01L27/02 ,  H02H9/04

Abstract: A microelectronic device has a protected line and a reference line, and an active field effect transistor (FET) coupled between the protected line and the reference line. The microelectronic device includes an electrostatic discharge (ESD) trigger circuit coupled to the gate of the active FET, to turn on the active FET when an ESD event occurs on the protected line. The microelectronic device further includes a transient detection circuit having a high bandwidth detector, an ESD detector, and an output driver. The ESD detector is configured to provide a CLEAR signal to the output driver when an ESD event occurs on the protected line. The output driver is configured to turn off the active FET when a voltage surge, which can damage the active FET, occurs on the protected line, but enable operation of the active FET by the ESD trigger circuit during an ESD event.