公开(公告)号：US09190462B2

公开(公告)日：2015-11-17

申请号：US14492331

申请日：2014-09-22

Applicant: Texas Instruments Deutschland GMBH ,  Texas Instruments Incorporated

Inventor： Christoph Andreas Othmar Dirnecker ,  Leif Christian Olsen

IPC: H01L29/00 ,  H01L49/02 ,  H01L23/522 ,  H01L27/01 ,  H01L21/768

CPC classification number: H01L28/24 ,  H01L21/76816 ,  H01L21/76895 ,  H01L23/5228 ,  H01L27/016 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a semiconductor device and a method of manufacturing an electronic device. A first conductive layer (first metal interconnect layer) is deposited. There is an insulating layer (first intermetal dielectric) layer deposited. A resistive layer is deposited on top of the insulating layer and structured in order to serve as a thin film resistor. A second insulating layer (second intermetal dielectric) is then deposited on top of the resistive layer. A first opening is etched into the insulating layers (first and second intermetal dielectric) down to the first conductive layer. A second opening is etched into the insulating layers (first and second intermetal dielectrics) down to the first conductive layer. A cross-sectional plane of the second opening is arranged such that it at least partially overlaps the resistive layer of the thin film resistor in a first direction.

Abstract translation: 本发明涉及一种半导体器件和一种制造电子器件的方法。 沉积第一导电层（第一金属互连层）。 存在沉积的绝缘层（第一金属间电介质）层。 电阻层沉积在绝缘层的顶部并被构造以便用作薄膜电阻器。 然后在电阻层的顶部上沉积第二绝缘层（第二金属间电介质）。 绝缘层（第一和第二金属间电介质）中的第一开口被蚀刻到第一导电层。 绝缘层（第一和第二金属间电介质）中的第二个开口被蚀刻到第一导电层。 第二开口的横截面被布置成使得其在第一方向上至少部分地与薄膜电阻器的电阻层重叠。

公开(公告)号：US10770538B2

公开(公告)日：2020-09-08

申请号：US15976357

申请日：2018-05-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christoph Andreas Othmar Dirnecker ,  Wolfgang Schwartz ,  Doug Weiser ,  Joel Martin Halbert ,  Joseph Anthony DeSantis ,  Karsten Jens Spinger

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/268

Abstract: A method of forming an electronic device includes forming an opening through a dielectric layer located over a first resistive layer, the first resistive layer having a first sheet resistance. A second resistive layer is deposited over the dielectric layer and into the opening. The second resistive layer has a second sheet resistance different from the first sheet resistance. A portion of the second resistive layer is removed, thereby forming first and second noncontiguous portions of the second resistive layer, wherein the second portion of the second resistive layer contacts the first resistive layer.

公开(公告)号：US20180019297A1

公开(公告)日：2018-01-18

申请号：US15209696

申请日：2016-07-13

Applicant: Texas Instruments Incorporated ,  TEXAS INSTRUMENTS DEUTSCHLAND GMBH

Inventor： Christoph Andreas Othmar Dirnecker ,  Wolfgang Schwartz ,  Doug Weiser ,  Joel Martin Halbert ,  Joseph Anthony DeSantis ,  Karsten Jens Spinger

IPC: H01L49/02 ,  H01L23/522 ,  H01L21/268 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/3205 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L28/24 ,  H01L21/0273 ,  H01L21/268 ,  H01L21/32051 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/528

Abstract: An integrated circuit includes a higher sheet resistance resistor and a lower sheet resistance resistor, disposed in a same level of dielectric layers of the integrated circuit. The higher sheet resistor has a body region and head regions in a higher sheet resistance layer. The lower sheet resistor has a body region and head regions in a lower sheet resistance layer, which is thicker than the higher sheet layer. The higher sheet resistor has an upper head layer contacting the higher sheet layer at each head region of the higher sheet layer. Each upper head layer has a same composition and thickness as the lower sheet layer of the lower sheet resistor. The lower sheet resistor is free of head layers over the lower sheet resistance layer.

公开(公告)号：US11676993B2

公开(公告)日：2023-06-13

申请号：US17014094

申请日：2020-09-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christoph Andreas Othmar Dirnecker ,  Wolfgang Schwartz ,  Doug Weiser ,  Joel Martin Halbert ,  Joseph Anthony DeSantis ,  Karsten Jens Spinger

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/268

CPC classification number: H01L28/24 ,  H01L21/0273 ,  H01L21/268 ,  H01L21/32139 ,  H01L23/5226 ,  H01L23/5228

Abstract: In one example an electronic device includes a first resistor and a second resistor. The first resistor includes a first resistive layer located over a substrate, the first resistive layer having a first sheet resistance. The second resistor includes a first portion of a second resistive layer located over the substrate, the second resistive layer having a second sheet resistance different from the first sheet resistance. The first resistive layer is located between the substrate and a second noncontiguous portion of the second resistive layer.

公开(公告)号：US20180261664A1

公开(公告)日：2018-09-13

申请号：US15976357

申请日：2018-05-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christoph Andreas Othmar Dirnecker ,  Wolfgang Schwartz ,  Doug Weiser ,  Joel Martin Halbert ,  Joseph Anthony DeSantis ,  Karsten Jens Spinger

IPC: H01L49/02 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/268 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L28/24 ,  H01L21/0273 ,  H01L21/268 ,  H01L21/32139 ,  H01L23/5226 ,  H01L23/5228

Abstract: An electronic device includes a first resistor and a second resistor. The first resistor includes a first resistive layer located over a substrate and having a first sheet resistance. The second resistor includes a first portion of a second resistive layer located over the substrate and having a second sheet resistance that is different from the first sheet resistance. The first resistive layer is located between the substrate and a second noncontiguous portion of the second resistive layer.

公开(公告)号：US09991329B2

公开(公告)日：2018-06-05

申请号：US15209696

申请日：2016-07-13

Applicant: Texas Instruments Incorporated

Inventor： Christoph Andreas Othmar Dirnecker ,  Wolfgang Schwartz ,  Doug Weiser ,  Joel Martin Halbert ,  Joseph Anthony DeSantis ,  Karsten Jens Spinger

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/528 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/268

CPC classification number: H01L28/24 ,  H01L21/0273 ,  H01L21/268 ,  H01L21/32051 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/528

Abstract: An integrated circuit includes a higher sheet resistance resistor and a lower sheet resistance resistor, disposed in a same level of dielectric layers of the integrated circuit. The higher sheet resistor has a body region and head regions in a higher sheet resistance layer. The lower sheet resistor has a body region and head regions in a lower sheet resistance layer, which is thicker than the higher sheet layer. The higher sheet resistor has an upper head layer contacting the higher sheet layer at each head region of the higher sheet layer. Each upper head layer has a same composition and thickness as the lower sheet layer of the lower sheet resistor. The lower sheet resistor is free of head layers over the lower sheet resistance layer.