公开(公告)号：US20190131983A1

公开(公告)日：2019-05-02

申请号：US16151752

申请日：2018-10-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dinesh JAIN ,  Markus Friedrich DIETL

IPC: H03L7/197 ,  H03K23/68

CPC classification number: H03L7/1976 ,  H03K23/68

Abstract: A full quadrant analog interpolator used in a fractional clock generator. A quadrature clock signal with minimal jitter is provided to the full quadrant analog interpolator. The full quadrant analog interpolator uses a series of switches and current sources to develop a differential output signal based on a digital input value, thus allowing digital control of the delay developed by the full quadrant analog interpolator. The differential output of the full quadrant analog interpolator is provided to multi-stage comparator. The output of the multi-stage comparator is provided to an integer divider to provide the final output clock. A digital control section utilizes a ΣΔ modulator and a summer to utilize an input N.α control input which provides the desired fractional division amount to provide a signal to a phase accumulator. The output of the phase accumulator is the digital control or β value of the full quadrant analog interpolator.

公开(公告)号：US20180097512A1

公开(公告)日：2018-04-05

申请号：US15673166

申请日：2017-08-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srikanth MANIAN ,  Srinivas THEERTHAM ,  Jagdish CHAND ,  Dinesh JAIN

IPC: H03K5/26 ,  H03K5/135 ,  H03L7/081 ,  H03L7/08 ,  H03L7/07 ,  H03L7/18 ,  H03K5/15

CPC classification number: H03K5/26 ,  H03K5/135 ,  H03K5/1502 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/081 ,  H03L7/18

Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.