公开(公告)号：US20210391866A1

公开(公告)日：2021-12-16

申请号：US17128791

申请日：2020-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivas THEERTHAM ,  Jagdish CHAND ,  Yogesh DARWHEKAR ,  Subhashish MUKHERJEE ,  Jayawardan JANARDHANAN ,  Uday Kiran MEDA ,  Arpan Sureshbhai THAKKAR ,  Apoorva BHATIA ,  Pranav KUMAR

IPC: H03L7/23 ,  H03L7/099 ,  H03L7/085 ,  H03M1/66

Abstract: A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.

公开(公告)号：US20220038056A1

公开(公告)日：2022-02-03

申请号：US17493922

申请日：2021-10-05

Applicant: Texas Instruments Incorporated

Inventor： Srinivas THEERTHAM ,  Srikanth MANIAN ,  Uday Kiran MEDA

IPC: H03B5/12 ,  H03L7/099

Abstract: A system includes a data path and a phase-locked loop (PLL) coupled to the data path. The system also includes a voltage-controlled oscillator (VCO) coupled to the PLL. The VCO includes an LC circuit with first and second differential output terminals. The VCO also includes a first resistor coupled between the first differential output terminal and drain terminals of a first pair of complementary metal-oxide semiconductor (CMOS) transistors. The VCO also includes a second resistor coupled between the second differential output terminal and drain terminals of a second pair of CMOS transistors.

公开(公告)号：US20180097512A1

公开(公告)日：2018-04-05

申请号：US15673166

申请日：2017-08-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srikanth MANIAN ,  Srinivas THEERTHAM ,  Jagdish CHAND ,  Dinesh JAIN

IPC: H03K5/26 ,  H03K5/135 ,  H03L7/081 ,  H03L7/08 ,  H03L7/07 ,  H03L7/18 ,  H03K5/15

CPC classification number: H03K5/26 ,  H03K5/135 ,  H03K5/1502 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/081 ,  H03L7/18

Abstract: In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.