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    FLL oscillator/clock with an FLL control loop including a switched capacitor resistive divider
    1.
    发明授权
    FLL oscillator/clock with an FLL control loop including a switched capacitor resistive divider 有权
    FLL振荡器/时钟，带FLL控制回路，包括开关电容电阻分压器

    公开(公告)号：US09455721B2

    公开(公告)日：2016-09-27

    申请号：US14588293

    申请日：2014-12-31

    Applicant: Texas Instruments Incorporated

    Inventor： Divyasree J. ,  Anant Shankar Kamath

    IPC: H03L7/06 ,  H03K3/03 ,  H03K4/06 ,  H03L7/00

    CPC classification number: H03L7/06 ,  H03K3/0231 ,  H03K3/0315 ,  H03K3/84 ,  H03K4/06 ,  H03L7/00

    Abstract: An FLL (frequency locked loop) oscillator/clock generator includes a free-running oscillator (such as a ring oscillator), and generates an FLL_clk with an FLL-controlled frequency fOSC. The FLL control loop includes a switched capacitor resistor divider that converts fOSC to a resistance, generating an FLL feedback voltage Vfosc used to generate a loop control signal OSC_cntrl input to the oscillator. In response, the oscillator frequency locks FLL_clk to fosc. In an example implementation, the FLL oscillator/clock operates with spread spectrum clocking (SSC) that provides triangular SSC modulation based on a truncated RC transition voltage generated as a negative feedback to an RC relaxation oscillator, with truncation based on switched tripping threshold voltages generated a positive feedback to the RC relaxation oscillator.

    Abstract translation: FLL（锁频环）振荡器/时钟发生器包括一个自由振荡器（例如环形振荡器），并产生具有FLL控制频率fOSC的FLL_clk。 FLL控制回路包括将fOSC转换为电阻的开关电容电阻分压器，产生用于产生输入到振荡器的回路控制信号OSC_cntrl的FLL反馈电压Vfosc。 作为响应，振荡器频率将FLL_clk锁定到fosc。 在示例实现中，FLL振荡器/时钟以扩频时钟（SSC）工作，该扩频频谱时钟（SSC）基于产生为RC松弛振荡器的负反馈的截断RC转换电压提供三角形SSC调制，基于产生的切换跳闸阈值电压进行截断 对RC松弛振荡器的正反馈。

    Timing correction in a communication system
    4.
    发明授权
    Timing correction in a communication system 有权

    公开(公告)号：US10122524B2

    公开(公告)日：2018-11-06

    申请号：US15899658

    申请日：2018-02-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Anant Shankar Kamath ,  Divyasree J.

    IPC: H04L7/00 ,  H04L25/02 ,  H04L25/08

    Abstract: One example includes a communication system. The system includes a data transmitter configured to generate a digital communication signal and a data receiver configured to receive the digital communication signal. The system also includes a pulse-width distortion (PWD) correction circuit arranged between the data transmitter and the data receiver and being configured to adjust at least one timing parameter associated with the communication signal.

    FLL OSCILLATOR/CLOCK WITH AN FLL CONTROL LOOP INCLUDING A SWITCHED CAPACITOR RESISTIVE DIVIDER
    8.
    发明申请
    FLL OSCILLATOR/CLOCK WITH AN FLL CONTROL LOOP INCLUDING A SWITCHED CAPACITOR RESISTIVE DIVIDER 有权
    FLL振荡器/具有FLL控制环的时钟，包括开关电容电阻分压器

    公开(公告)号：US20160105187A1

    公开(公告)日：2016-04-14

    申请号：US14588293

    申请日：2014-12-31

    Applicant: Texas Instruments Incorporated

    Inventor： Divyasree J. ,  Anant Shankar Kamath

    IPC: H03L7/06 ,  H03K4/06 ,  H03K3/03

    CPC classification number: H03L7/06 ,  H03K3/0231 ,  H03K3/0315 ,  H03K3/84 ,  H03K4/06 ,  H03L7/00

    Abstract: An FLL (frequency locked loop) oscillator/clock generator includes a free-running oscillator (such as a ring oscillator), and generates an FLL_clk with an FLL-controlled frequency fOSC. The FLL control loop includes a switched capacitor resistor divider that converts fOSC to a resistance, generating an FLL feedback voltage Vfosc used to generate a loop control signal OSC_cntrl input to the oscillator. In response, the oscillator frequency locks FLL_clk to fosc. In an example implementation, the FLL oscillator/clock operates with spread spectrum clocking (SSC) that provides triangular SSC modulation based on a truncated RC transition voltage generated as a negative feedback to an RC relaxation oscillator, with truncation based on switched tripping threshold voltages generated a positive feedback to the RC relaxation oscillator.

    Abstract translation: FLL（锁频环）振荡器/时钟发生器包括一个自由振荡器（例如环形振荡器），并产生具有FLL控制频率fOSC的FLL_clk。 FLL控制回路包括将fOSC转换为电阻的开关电容电阻分压器，产生用于产生输入到振荡器的回路控制信号OSC_cntrl的FLL反馈电压Vfosc。 作为响应，振荡器频率将FLL_clk锁定到fosc。 在示例实现中，FLL振荡器/时钟以扩频时钟（SSC）工作，该扩频频谱时钟（SSC）基于产生为RC松弛振荡器的负反馈的截断RC转换电压提供三角形SSC调制，基于产生的切换跳闸阈值电压进行截断 对RC松弛振荡器的正反馈。

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