公开(公告)号：US10511848B2

公开(公告)日：2019-12-17

申请号：US15000566

申请日：2016-01-19

Applicant: Texas Instruments Incorporated

Inventor： Vivekanand Chengalvala ,  Djordje Senicic

IPC: H04N11/02 ,  H04N19/423 ,  H04N19/42 ,  H04N19/40 ,  H04N19/44 ,  H04N19/70

Abstract: An adaptive transcoder is provided that includes a shared memory containing a plurality of decoder buffers to store incoming data packets, a plurality of decoder instances to control a decoding process to generate image raw data based on the incoming data packets, and a plurality of encoder instances configured to control an encoding process to generate outgoing packets based on the image raw data; and a data processing element containing a plurality of processing cores, and a core controller. Each decoder instance is paired with an encoder instance; and each decoder buffer is associated with a decoder instance. Each decoder buffer includes a monitoring element to monitor a respective decoder buffer, and provide buffer data corresponding to the status of the decoder buffer. Each encoder instance is associated with a processing core; and the core controller uses the buffer data to associate each decoder instance with a processing core.

公开(公告)号：US09788011B2

公开(公告)日：2017-10-10

申请号：US15403311

申请日：2017-01-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mujibur Rahman ,  Djordje Senicic ,  Timothy D. Anderson

IPC: G06F9/30 ,  H04N19/43 ,  H04N19/513 ,  H04N19/56 ,  H04N19/433

CPC classification number: H04N19/56 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3853 ,  G06F9/3893 ,  G06F2207/5442 ,  H04N19/433 ,  H04N19/521

Abstract: This invention is a digital signal processor form plural sums of absolute values (SAD) in a single operation. An operational unit performing a sum of absolute value operation comprising two sets of a plurality of rows, each row producing a SAD output. Plural absolute value difference units receive corresponding packed candidate pixel data and packed reference pixel data. A row summer sums the output of the absolute value difference units in the row. The candidate pixels are offset relative to the reference pixels by one pixel for each succeeding row in a set of rows. The two sets of rows operate on opposite halves of the candidate pixels packed within an instruction specified operand. The SAD operations can be performed on differing data widths employing carry chain control in the absolute difference unit and the row summers.

公开(公告)号：US09582273B2

公开(公告)日：2017-02-28

申请号：US14327002

申请日：2014-07-09

Applicant: Texas Instruments Incorporated

Inventor： Mujibur Rahman ,  Djordje Senicic ,  Timothy D. Anderson

IPC: G06F9/30 ,  G06F9/38

CPC classification number: H04N19/56 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3853 ,  G06F9/3893 ,  G06F2207/5442 ,  H04N19/433 ,  H04N19/521

Abstract: This invention is a digital signal processor form plural sums of absolute values (SAD) in a single operation. An operational unit performing a sum of absolute value operation comprising two sets of a plurality of rows, each row producing a SAD output. Plural absolute value difference units receive corresponding packed candidate pixel data and packed reference pixel data. A row summer sums the output of the absolute value difference units in the row. The candidate pixels are offset relative to the reference pixels by one pixel for each succeeding row in a set of rows. The two sets of rows operate on opposite halves of the candidate pixels packed within an instruction specified operand. The SAD operations can be performed on differing data widths employing carry chain control in the absolute difference unit and the row summers.

Abstract translation: 本发明是在单个操作中形成多个绝对值（SAD）的数字信号处理器。 执行包括两组多行的绝对值操作之和的操作单元，每行产生SAD输出。 多个绝对值差分单元接收相应的压缩候选像素数据和压缩参考像素数据。 行夏天对行中的绝对值差单位的输出求和。 候选像素相对于参考像素相对于一组行中的每个后续行偏移一个像素。 两组行在包含在指令指定操作数中的候选像素的相对的两半上进行操作。 可以使用绝对差分单位和行夏季的进位链控制在不同的数据宽度上执行SAD操作。

公开(公告)号：US20170150175A1

公开(公告)日：2017-05-25

申请号：US15403311

申请日：2017-01-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mujibur Rahman ,  Djordje Senicic ,  Timothy D. Anderson

IPC: H04N19/56 ,  H04N19/433 ,  H04N19/513

CPC classification number: H04N19/56 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3853 ,  G06F9/3893 ,  G06F2207/5442 ,  H04N19/433 ,  H04N19/521

Abstract: This invention is a digital signal processor form plural sums of absolute values (SAD) in a single operation. An operational unit performing a sum of absolute value operation comprising two sets of a plurality of rows, each row producing a SAD output. Plural absolute value difference units receive corresponding packed candidate pixel data and packed reference pixel data. A row summer sums the output of the absolute value difference units in the row. The candidate pixels are offset relative to the reference pixels by one pixel for each succeeding row in a set of rows. The two sets of rows operate on opposite halves of the candidate pixels packed within an instruction specified operand. The SAD operations can be performed on differing data widths employing carry chain control in the absolute difference unit and the row summers.

公开(公告)号：US20160134880A1

公开(公告)日：2016-05-12

申请号：US15000566

申请日：2016-01-19

Applicant: Texas Instruments Incorporated

Inventor： Vivekanand Chengalvala ,  Djordje Senicic

IPC: H04N19/423 ,  H04N19/44 ,  H04N19/70 ,  H04N19/40

CPC classification number: H04N19/423 ,  H04N19/40 ,  H04N19/42 ,  H04N19/44 ,  H04N19/70

Abstract: An adaptive transcoder is provided that includes a shared memory containing a plurality of decoder buffers to store incoming data packets, a plurality of decoder instances to control a decoding process to generate image raw data based on the incoming data packets, and a plurality of encoder instances configured to control an encoding process to generate outgoing packets based on the image raw data; and a data processing element containing a plurality of processing cores, and a core controller. Each decoder instance is paired with an encoder instance; and each decoder buffer is associated with a decoder instance. Each decoder buffer includes a monitoring element to monitor a respective decoder buffer, and provide buffer data corresponding to the status of the decoder buffer. Each encoder instance is associated with a processing core; and the core controller uses the buffer data to associate each decoder instance with a processing core.

Abstract translation: 提供了一种自适应代码转换器，其包括：包含多个解码器缓冲器以存储输入数据分组的共享存储器;多个解码器实例，用于控制解码过程以基于输入数据分组生成图像原始数据;以及多个编码器实例 被配置为基于所述图像原始数据来控制编码处理以生成输出分组; 以及包含多个处理核心的数据处理元件和核心控制器。 每个解码器实例与编码器实例配对; 并且每个解码器缓冲器与解码器实例相关联。 每个解码器缓冲器包括监视元件以监视相应的解码器缓冲器，并提供对应于解码器缓冲器的状态的缓冲器数据。 每个编码器实例与处理核心相关联; 并且核心控制器使用缓冲器数据将每个解码器实例与处理核心相关联。

公开(公告)号：US20150082004A1

公开(公告)日：2015-03-19

申请号：US14327002

申请日：2014-07-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mujibur Rahman ,  Djordje Senicic ,  Timothy D. Anderson

IPC: G06F9/30

CPC classification number: H04N19/56 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3853 ,  G06F9/3893 ,  G06F2207/5442 ,  H04N19/433 ,  H04N19/521

Abstract: This invention is a digital signal processor form plural sums of absolute values (SAD) in a single operation. An operational unit performing a sum of absolute value operation comprising two sets of a plurality of rows, each row producing a SAD output. Plural absolute value difference units receive corresponding packed candidate pixel data and packed reference pixel data. A row summer sums the output of the absolute value difference units in the row. The candidate pixels are offset relative to the reference pixels by one pixel for each succeeding row in a set of rows. The two sets of rows operate on opposite halves of the candidate pixels packed within an instruction specified operand. The SAD operations can be performed on differing data widths employing carry chain control in the absolute difference unit and the row summers.

Abstract translation: 本发明是在单个操作中形成多个绝对值（SAD）的数字信号处理器。 执行包括两组多行的绝对值操作之和的操作单元，每行产生SAD输出。 多个绝对值差分单元接收相应的压缩候选像素数据和压缩参考像素数据。 行夏天对行中的绝对值差单位的输出求和。 候选像素相对于参考像素相对于一组行中的每个后续行偏移一个像素。 两组行在包含在指令指定操作数中的候选像素的相对的两半上进行操作。 可以使用绝对差分单位和行夏季的进位链控制在不同的数据宽度上执行SAD操作。