公开(公告)号：US20250105104A1

公开(公告)日：2025-03-27

申请号：US18475563

申请日：2023-09-27

Applicant: Texas Instruments Incorporated

Inventor： Li Jiang ,  Rey Javier ,  Guangxu Li ,  Enis Tuncer

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: An electronic device includes a package structure having four lateral corners, a semiconductor die at least partially enclosed inside the package structure and attached to a die attach pad, conductive leads at least partially exposed outside the package structure along the four lateral sides, a first one of the conductive leads electrically connected to the semiconductor die, an instance of a first conductive feature partially exposed outside the package structure at each of the corners, and an instance of a second conductive feature partially exposed outside the package structure and contacting a respective instance of the first conductive feature at each of the corners, the instance of the second conductive feature exposed outside the package structure along the first side.

公开(公告)号：US20240332433A1

公开(公告)日：2024-10-03

申请号：US18193037

申请日：2023-03-30

Applicant: Texas Instruments Incorporated

Inventor： Li Jiang ,  Makarand Ramkrishna Kulkarni

IPC: H01L29/94 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/64 ,  H01L29/66

CPC classification number: H01L29/945 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L21/76838 ,  H01L23/642 ,  H01L28/40 ,  H01L29/66181

Abstract: An electronic device includes a semiconductor die having a side, first conductive terminals along a first portion of the side, and second conductive terminals along a second portion of the side, a substrate having conductive features facing the first portion of the side of the semiconductor die and electrically coupled to respective ones of the first conductive terminals, a capacitor die or a ceramic capacitor having conductive capacitor terminals facing the second portion of the side of the semiconductor die and electrically coupled to respective ones of the second conductive terminals, and a package structure that at least partially encloses the semiconductor die, the substrate and the capacitor die or ceramic capacitor.

公开(公告)号：US11587891B2

公开(公告)日：2023-02-21

申请号：US17335010

申请日：2021-05-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Li Jiang ,  Rajen Manicon Murugan

IPC: H01L23/58 ,  H01L23/552 ,  H01L23/00

Abstract: In examples, a semiconductor package comprises a ceramic substrate and first and second metal layers covered by the ceramic substrate. The first metal layer is configured to carry signals at least in a 20 GHz to 28 GHz frequency range. The package comprises a semiconductor die positioned above the first and second metal layers and coupled to the first metal layer. The package comprises a ground shield positioned in a horizontal plane between the semiconductor die and the first metal layer, the ground shield including an orifice above a portion of the first metal layer. The package includes a metal seal ring coupled to a top surface of the ceramic substrate, the metal seal ring having a segment that is vertically aligned with a segment of the ground shield. The segment of the ground shield is between the orifice of the ground shield and a horizontal center of the ground shield. The package comprises a metal lid coupled to a top surface of the metal seal ring.

公开(公告)号：US11881460B2

公开(公告)日：2024-01-23

申请号：US18172208

申请日：2023-02-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Li Jiang ,  Rajen Manicon Murugan

IPC: H01L23/00 ,  H01L23/552 ,  H01L23/58 ,  H01L21/50 ,  H01L21/52

CPC classification number: H01L23/585 ,  H01L21/50 ,  H01L21/52 ,  H01L23/552 ,  H01L23/562 ,  H01L23/564

Abstract: In examples, a semiconductor package comprises a ceramic substrate and first and second metal layers covered by the ceramic substrate. The first metal layer is configured to carry signals at least in a 20 GHz to 28 GHz frequency range. The package comprises a semiconductor die positioned above the first and second metal layers and coupled to the first metal layer. The package comprises a ground shield positioned in a horizontal plane between the semiconductor die and the first metal layer, the ground shield including an orifice above a portion of the first metal layer. The package includes a metal seal ring coupled to a top surface of the ceramic substrate, the metal seal ring having a segment that is vertically aligned with a segment of the ground shield. The segment of the ground shield is between the orifice of the ground shield and a horizontal center of the ground shield. The package comprises a metal lid coupled to a top surface of the metal seal ring.

公开(公告)号：US20240006267A1

公开(公告)日：2024-01-04

申请号：US17809808

申请日：2022-06-29

Applicant: Texas Instruments Incorporated

Inventor： Li Jiang ,  Yiqi Tang ,  Jie Chen ,  Rajen M. Murugan

IPC: H01L23/433 ,  H01L23/15 ,  H01L23/13 ,  H01L21/48

CPC classification number: H01L23/433 ,  H01L23/15 ,  H01L23/13 ,  H01L21/4882 ,  H01L24/16

Abstract: An example semiconductor package comprises a ceramic header having a top surface and a cavity formed within the ceramic header. The cavity is open at the top surface. A semiconductor die is mounted within the cavity of the ceramic header. A lid structure is coupled to the top surface of the ceramic header. The lid structure and ceramic header form a portion of a package enclosing the semiconductor die. One or more silver tubes are in contact with a first surface of the semiconductor die and with a first surface of the lid structure. A seal ring is located between the top surface of the ceramic header and the lid structure. The seal ring couples the lid structure to the ceramic header. The one or more silver tubes are hollow and filled with a getter material.

公开(公告)号：US12040265B2

公开(公告)日：2024-07-16

申请号：US17387794

申请日：2021-07-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yiqi Tang ,  Rajen Manicon Murugan ,  Li Jiang

IPC: H01L23/498 ,  H01L23/13 ,  H01P3/02 ,  H05K1/02

CPC classification number: H01L23/49838 ,  H01L23/13 ,  H01L23/49805 ,  H01L23/49822 ,  H01P3/02 ,  H05K1/0243

Abstract: In examples, a semiconductor package comprises a ceramic substrate and a horizontal metal layer covered by the ceramic substrate. The metal layer is configured to carry signals in the 5 GHz to 38 GHz frequency range. The package also includes a vertical castellation on an outer surface of the ceramic substrate, the castellation coupled to the metal layer and having a height ranging from 0.10 mm to 0.65 mm.

公开(公告)号：US20230352387A1

公开(公告)日：2023-11-02

申请号：US17733414

申请日：2022-04-29

Applicant: Texas Instruments Incorporated

Inventor： Li Jiang ,  Yiqi Tang ,  Usman Mahmood Chaudhry ,  Thiha Shwe

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/66

CPC classification number: H01L23/49827 ,  H01L23/49816 ,  H01L24/17 ,  H01L22/34 ,  H01L2224/1413 ,  H01L2224/1403

Abstract: An example semiconductor package comprises an integrated circuit die having a first surface with a first array of electrode pads. A laminate substrate has an upper surface with a second array of electrode pads. The electrode pads of the first array are connected to corresponding electrode pads of the second array using a solder bump. The laminate substrate has a lower surface with a third array of electrode pads. The electrodes of the third array are coupled to corresponding electrodes of the second array by a laminate wiring structure within the laminate substrate. A first electrode on the lower surface is coupled to a second electrode on the lower surface by a chain of vias through the laminate substrate. The chain of vias is not connected to the integrated circuit die.

公开(公告)号：US20240304517A1

公开(公告)日：2024-09-12

申请号：US18180024

申请日：2023-03-07

Applicant: Texas Instruments Incorporated

Inventor： Li Jiang ,  Jie Chen ,  Yutaka Suzuki ,  Rajen Murugan

IPC: H01L23/373 ,  H01L21/56 ,  H01L21/784 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01L23/3737 ,  H01L21/565 ,  H01L21/784 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L25/165 ,  H01L2224/08235 ,  H01L2224/273 ,  H01L2224/29193 ,  H01L2224/32221 ,  H01L2224/94 ,  H01L2924/182

Abstract: An electronic device includes: a semiconductor die having opposite first and second sides and a conductive terminal along the first side; a conductive lead electrically coupled to the conductive terminal; a package structure that forms a top side of the electronic device and encloses a portion of the semiconductor die, the package structure including a first molding compound having a first thermal conductivity; and a thermally conductive layer on at least a portion of the second side of the semiconductor die, the thermally conductive layer including a second molding compound having a second thermal conductivity that is greater than the first thermal conductivity.

公开(公告)号：US20240128170A1

公开(公告)日：2024-04-18

申请号：US17965583

申请日：2022-10-13

Applicant: Texas Instruments Incorporated

Inventor： Yiqi Tang ,  Li Jiang ,  Rajen Murugan ,  Robert John Falcone ,  Usman Mahmood Chaudhry

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/373 ,  H01L23/66

CPC classification number: H01L23/49805 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3736 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L2223/6622 ,  H01L2223/6644 ,  H01L2223/6677 ,  H01L2223/6688

Abstract: An electronic device includes a rectangular ceramic package structure having opposite first and second sides, an interior cavity that extends to an opening in the second side, opposite third and fourth sides spaced along a first direction, opposite fifth and sixth sides spaced along an orthogonal second direction, and non-conductive indents extending into the third and fourth sides. The device also includes a semiconductor die in the cavity, a lid that covers the opening and seals the cavity, a conductive terminal having a planar side exposed along the first side that is electrically coupled to a circuit of the semiconductor die and extends to a first one of the non-conductive indents, and conductive pins spaced apart from the conductive terminal and extending outward from the first side of the ceramic package structure along a third direction.