公开(公告)号：US10187071B2

公开(公告)日：2019-01-22

申请号：US15387636

申请日：2016-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Himanshu Arora ,  Siraj Akhtar ,  Lu Sun ,  Hamid Safiri ,  Wenjing Lu ,  Nikolaus Klemmer

IPC: H03L7/099 ,  H03L7/10 ,  H03L1/02

Abstract: A PLL including a VCO with a variable capacitance (such as an LC VCO) including a switched capacitor bank and a varactor, the PLL providing lock range extension over temperature using dynamic capacitor bank switching to dynamically adjust varactor set point based on junction temperature. The varactor is responsive to the Vctrl control voltage to adjust a capacitance of the variable capacitance to control the phase of the PLL signal. Compensation circuitry dynamically adjusts varactor set point by dynamically switching the capacitor bank based in a junction temperature associated with the PLL circuitry, thereby extending PLL lock range over temperature.

公开(公告)号：US20170264302A1

公开(公告)日：2017-09-14

申请号：US15387636

申请日：2016-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Himanshu Arora ,  Siraj Akhtar ,  Lu Sun ,  Hamid Safiri ,  Wenjing Lu ,  Nikolaus Klemmer

IPC: H03L1/02 ,  H03L7/10

CPC classification number: H03L7/103 ,  H03L1/021 ,  H03L1/026 ,  H03L7/099 ,  H03L7/10 ,  H03L2207/06

Abstract: A multi-ladder DAC includes first and second resistor ladders, with a switch-interconnect. The switch-interconnect includes a second set of switches connected between each node of the first ladder and the top and bottom tap points of the second ladder. All other second ladder tap points are part of a loop tied to the nodes above and below each resistor through a second set of switches. Because no current flows through the switches that tie the top and bottom second-ladder tap points to the nodes of the first ladder, avoiding IRswitch error, thereby improving DNL.