公开(公告)号：US11436024B2

公开(公告)日：2022-09-06

申请号：US16700254

申请日：2019-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Denis Roland Beaudoin ,  Gregory Raymond Shurtz ,  Santhanakrishnan Badri Narayanan ,  Mark Adrian Bryans ,  Mihir Narendra Mody ,  Jason A. T. Jones ,  Jayant Thakur

IPC: G06F9/4401 ,  H04L45/00 ,  H04L47/32 ,  G06F13/28 ,  H04L49/351

Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.

公开(公告)号：US20240126560A1

公开(公告)日：2024-04-18

申请号：US18395697

申请日：2023-12-25

Applicant: Texas Instruments Incorporated

Inventor： Sriramakrishnan Govindarajan ,  Denis Roland Beaudoin ,  Gregory Raymond Shurtz ,  Santhanakrishnan Badri Narayanan ,  Mark Adrian Bryans ,  Mihir Narendra Mody ,  Jason A.T. Jones ,  Jayant Thakur

IPC: G06F9/4401 ,  G06F13/28 ,  H04L45/00 ,  H04L47/32 ,  H04L49/351

CPC classification number: G06F9/4418 ,  G06F9/4406 ,  G06F13/28 ,  H04L45/54 ,  H04L45/66 ,  H04L47/32 ,  H04L49/351

Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.

公开(公告)号：US11853772B2

公开(公告)日：2023-12-26

申请号：US17888533

申请日：2022-08-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriramakrishnan Govindarajan ,  Denis Roland Beaudoin ,  Gregory Raymond Shurtz ,  Santhanakrishnan Badri Narayanan ,  Mark Adrian Bryans ,  Mihir Narendra Mody ,  Jason A. T. Jones ,  Jayant Thakur

IPC: G06F9/4401 ,  H04L45/00 ,  H04L47/32 ,  G06F13/28 ,  H04L49/351

CPC classification number: G06F9/4418 ,  G06F9/4406 ,  G06F13/28 ,  H04L45/54 ,  H04L45/66 ,  H04L47/32 ,  H04L49/351

Abstract: An Ethernet switch and a switch microcontroller or CPU are integrated onto a system-on-a-chip (SoC). The Ethernet switch remains independently operating at full speed even though the remainder of the SoC is being reset or is otherwise nonoperational. The Ethernet switch is on a separated power and clock domain from the remainder of the integrated SoC. A warm reset signal is trapped by control microcontroller (MCU) to allow the switch CPU to isolate the Ethernet switch and save state. When the Ethernet switch is isolated and operating independently, the warm reset request is provided to the other entities on the integrated SoC. When warm reset is completed, the state is restored and the various DMA and flow settings redeveloped in the integrated SoC to allow return to normal operating condition.