公开(公告)号：US20210349827A1

公开(公告)日：2021-11-11

申请号：US17384864

申请日：2021-07-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai CHIRCA ,  Joseph R. M. ZBICIAK ,  Matthew D. PIERSON

IPC: G06F12/0897 ,  G06F12/0811 ,  G06F12/0862

Abstract: A prefetch unit generates a prefetch address in response to an address associated with a memory read request received from the first or second cache. The prefetch unit includes a prefetch buffer that is arranged to store the prefetch address in an address buffer of a selected slot of the prefetch buffer, where each slot of the prefetch unit includes a buffer for storing a prefetch address, and two sub-slots. Each sub-slot includes a data buffer for storing data that is prefetched using the prefetch address stored in the slot, and one of the two sub-slots of the slot is selected in response to a portion of the generated prefetch address. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.

公开(公告)号：US20230418759A1

公开(公告)日：2023-12-28

申请号：US18463101

申请日：2023-09-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai CHIRCA ,  Joseph R. M. ZBICIAK ,  Matthew D. PIERSON

IPC: G06F12/0897 ,  G06F12/0811 ,  G06F12/0862

CPC classification number: G06F12/0897 ,  G06F12/0811 ,  G06F12/0862 ,  G06F2212/6028 ,  G06F2212/602 ,  G06F12/0886

Abstract: A prefetch unit includes multiple memories; and a memory controller coupled to the multiple memories. The memory controller includes a prefetch stream filter and a prefetch buffer. The prefetch stream filter includes a first set of address slots and a set of direction prediction fields, each of which is associated with a respective one of the address slots of the first set of address slots. The prefetch buffer includes a set of buffer slots, each slot of the set of buffer slots including an address field, a direction prediction field, a data pending field, a data valid field, and a set of sub-slots configured to store data, wherein each address field of each slot of the set of buffer slots is configured to store at least a portion of an address associated with the corresponding slot.

公开(公告)号：US20180293199A1

公开(公告)日：2018-10-11

申请号：US15903183

申请日：2018-02-23

Applicant: Texas Instruments Incorporated

Inventor： David M. THOMPSON ,  Timothy D. ANDERSON ,  Joseph R. M. ZBICIAK ,  Abhijeet A. CHACHAD ,  Kai CHIRCA ,  Matthew D. PIERSON

IPC: G06F13/40 ,  G06F13/42 ,  H04L12/801 ,  G06F13/364 ,  H04L12/819

CPC classification number: G06F13/404 ,  G06F13/364 ,  G06F13/42 ,  G06F13/4282 ,  H04L47/10 ,  H04L47/215 ,  H04L47/39

Abstract: This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.

公开(公告)号：US20200057723A1

公开(公告)日：2020-02-20

申请号：US16552418

申请日：2019-08-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kai CHIRCA ,  Joseph R. M. ZBICIAK ,  Matthew D. PIERSON

IPC: G06F12/0897 ,  G06F12/0862 ,  G06F12/0811

Abstract: A prefetch unit generates a prefetch address in response to an address associated with a memory read request received from the first or second cache. The prefetch unit includes a prefetch buffer that is arranged to store the prefetch address in an address buffer of a selected slot of the prefetch buffer, where each slot of the prefetch unit includes a buffer for storing a prefetch address, and two sub-slots. Each sub-slot includes a data buffer for storing data that is prefetched using the prefetch address stored in the slot, and one of the two sub-slots of the slot is selected in response to a portion of the generated prefetch address. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.

公开(公告)号：US20180239710A1

公开(公告)日：2018-08-23

申请号：US15899138

申请日：2018-02-19

Applicant: Texas Instruments Incorporated

Inventor： Kai CHIRCA ,  Joseph R. M. ZBICIAK ,  Matthew D. PIERSON

IPC: G06F12/0897 ,  G06F12/0862 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0886

CPC classification number: G06F12/0897 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3844 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0886 ,  G06F2212/602 ,  G06F2212/6022 ,  G06F2212/6028 ,  Y02D10/13

Abstract: A prefetch unit generates a prefetch address in response to an address associated with a memory read request received from the first or second cache. The prefetch unit includes a prefetch buffer that is arranged to store the prefetch address in an address buffer of a selected slot of the prefetch buffer, where each slot of the prefetch unit includes a buffer for storing a prefetch address, and two sub-slots. Each sub-slot includes a data buffer for storing data that is prefetched using the prefetch address stored in the slot, and one of the two sub-slots of the slot is selected in response to a portion of the generated prefetch address. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.