DRY ETCH PROCESS LANDING ON METAL OXIDE ETCH STOP LAYER OVER METAL LAYER AND STRUCTURE FORMED THEREBY

    公开(公告)号:US20200303202A1

    公开(公告)日:2020-09-24

    申请号:US16897357

    申请日:2020-06-10

    Abstract: A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.

    DRY ETCH PROCESS LANDING ON METAL OXIDE ETCH STOP LAYER OVER METAL LAYER AND STRUCTURE FORMED THEREBY

    公开(公告)号:US20190304796A1

    公开(公告)日:2019-10-03

    申请号:US15936434

    申请日:2018-03-27

    Abstract: A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.

    CORRUGATED CAPACITOR
    3.
    发明申请

    公开(公告)号:US20250105135A1

    公开(公告)日:2025-03-27

    申请号:US18472837

    申请日:2023-09-22

    Abstract: The present disclosure generally relates to a corrugated capacitor in an integrated circuit (IC). In an example, an IC includes a first corrugated conductive layer, a second corrugated conductive layer, and a corrugated dielectric layer. The first corrugated conductive layer and the second corrugated conductive layer are over a semiconductor substrate. The corrugated dielectric layer is between the first corrugated conductive layer and the second corrugated conductive layer. Various examples may achieve a larger surface areas for respective plates of a capacitor for a given lateral footprint of the capacitor.

    Multi-stacked capacitor
    4.
    发明授权

    公开(公告)号:US11869725B2

    公开(公告)日:2024-01-09

    申请号:US17537626

    申请日:2021-11-30

    CPC classification number: H01G4/40 H01G4/008 H01G4/30

    Abstract: A stacked capacitor includes a capacitor stack. The capacitor stack includes a base plate having a first surface and a second opposing surface, a first dielectric layer on or over the base plate, and a first conductive plate on or over the first dielectric layer. A second dielectric layer is on or over the first conductive plate. A second conductive plate on or over the second dielectric layer. The capacitor stack has at least one sloped side with at least one slope with respect to the second surface of the base plate.

    Dry etch process landing on metal oxide etch stop layer over metal layer and structure formed thereby

    公开(公告)号:US11195725B2

    公开(公告)日:2021-12-07

    申请号:US16897357

    申请日:2020-06-10

    Abstract: A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.

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