公开(公告)号：US09929744B2

公开(公告)日：2018-03-27

申请号：US15782052

申请日：2017-10-12

Applicant: Texas Instruments Incorporated

Inventor： Sundarrajan Rangachari ,  Desmond Pravin Martin Fernandes ,  Rakesh Channabasappa Yaraduyathinahalli

IPC: G06F12/00 ,  H03M7/30

CPC classification number: H03M7/30 ,  G06F3/06 ,  G06F13/00 ,  G06F2212/401 ,  H03M7/6047

Abstract: Disclosed embodiments include a system having a first memory for storing a plurality of data quantities, each data quantity consisting of a first number of bits, and a second memory for storing a plurality of compressed data quantities, each compressed data quantity consisting of a second number of bits that is less than the first number of bits. The system includes circuitry for reading data quantities from the first memory and for writing compressed data quantities, corresponding to respective read data quantities, to non-sequential addresses in the second memory. The circuitry for reading data quantities from the first memory is for reading along a read orientation selected from one of row-orientation or column-orientation from the first memory, and the circuitry for writing compressed data quantities in the second memory is for writing along a write orientation in the second memory that differs from the read orientation.

公开(公告)号：US09793918B2

公开(公告)日：2017-10-17

申请号：US14814617

申请日：2015-07-31

Applicant: Texas Instruments Incorporated

Inventor： Sundarrajan Rangachari ,  Desmond Pravin Martin Fernandes ,  Rakesh Channabasappa Yaraduyathinahalli

IPC: G06F12/00 ,  H03M7/30

Abstract: A digital data storage and retrieval system. The system has a first memory for storing a plurality of data quantities, and each data quantity, in the plurality of data quantities, consists of a first number of bits. The system also has a second memory for storing a plurality of compressed data quantities, and each compressed data quantity, in the plurality of compressed data quantities, consists of a second number of bits that is less than the first number of bits. The system also has circuitry for reading data quantities from the first memory and circuitry for writing compressed data quantities, corresponding to respective read data quantities, to non-sequential addresses in the second memory. The system also may include circuitry for reading compressed data quantities from the second memory, and circuitry for writing decompressed data quantities, corresponding to respective read compressed data quantities, to non-sequential addresses in the first memory.

公开(公告)号：US20190317855A1

公开(公告)日：2019-10-17

申请号：US16453081

申请日：2019-06-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Indu Prathapan ,  Prashanth Saraf ,  Desmond Pravin Martin Fernandes ,  Saket Jalan

IPC: G06F11/10 ,  G06F3/06 ,  G11C11/56 ,  G11C11/16 ,  G11C5/04 ,  H03M13/37 ,  H03M13/35 ,  H03M13/19 ,  G11C7/22 ,  G11C7/10

Abstract: In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.

公开(公告)号：US10372531B2

公开(公告)日：2019-08-06

申请号：US15653749

申请日：2017-07-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Indu Prathapan ,  Prashanth Saraf ,  Desmond Pravin Martin Fernandes ,  Saket Jalan

IPC: G06F11/10 ,  G11C5/04 ,  G06F3/06 ,  G11C11/16 ,  G11C11/56 ,  H03M13/35 ,  G11C7/10 ,  G11C7/22

Abstract: In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.

公开(公告)号：US10320412B2

公开(公告)日：2019-06-11

申请号：US15895721

申请日：2018-02-13

Applicant: Texas Instruments Incorporated

Inventor： Sundarrajan Rangachari ,  Desmond Pravin Martin Fernandes ,  Rakesh Channabasappa Yaraduyathinahalli

IPC: G06F3/06 ,  H03M7/30 ,  G06F13/00

Abstract: Disclosed embodiments include a system having a first memory, a second memory, circuitry that reads data quantities from the first memory along a first orientation, a compression engine that compresses each of the read data quantities to produce corresponding compressed data quantities, and circuitry that writes the compressed data quantities to the second memory along a second orientation which differs from the first orientation. The read data quantities have a first bit width and the compressed data quantities have a second bit width that is less than the first bit width.

公开(公告)号：US20160110113A1

公开(公告)日：2016-04-21

申请号：US14814617

申请日：2015-07-31

Applicant: Texas Instruments Incorporated

Inventor： Sundarrajan Rangachari ,  Desmond Pravin Martin Fernandes ,  Rakesh Channabasappa Yaraduyathinahalli

IPC: G06F3/06

CPC classification number: H03M7/30 ,  G06F3/06 ,  G06F13/00 ,  G06F2212/401 ,  H03M7/6047

Abstract: A digital data storage and retrieval system. The system has a first memory for storing a plurality of data quantities, and each data quantity, in the plurality of data quantities, consists of a first number of bits. The system also has a second memory for storing a plurality of compressed data quantities, and each compressed data quantity, in the plurality of compressed data quantities, consists of a second number of bits that is less than the first number of bits. The system also has circuitry for reading data quantities from the first memory and circuitry for writing compressed data quantities, corresponding to respective read data quantities, to non-sequential addresses in the second memory. The system also may include circuitry for reading compressed data quantities from the second memory, and circuitry for writing decompressed data quantities, corresponding to respective read compressed data quantities, to non-sequential addresses in the first memory.

Abstract translation: 数字数据存储和检索系统。 该系统具有用于存储多个数据量的第一存储器，并且多个数据量中的每个数据量由第一位数组成。 该系统还具有用于存储多个压缩数据量的第二存储器，并且多个压缩数据量中的每个压缩数据量由小于第一位数的第二位数组成。 该系统还具有用于从第一存储器读取数据量的电路和用于将对应于各个读取数据量的压缩数据量写入第二存储器中的非顺序地址的电路。 该系统还可以包括用于从第二存储器读取压缩数据量的电路，以及用于将对应于各个读取的压缩数据量的解压缩数据量写入第一存储器中的非顺序地址的电路。