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公开(公告)号：US11962276B2
公开(公告)日：2024-04-16
申请号：US17501210
申请日：2021-10-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Vadim Valerievich Ivanov , Srinivas Kumar Pulijala
CPC classification number: H03F3/393 , H03F3/45179 , H03F2200/165 , H03F2200/261 , H03F2200/271
Abstract: In examples of a chopper operational amplifier, a current control circuit comprises a pair of voltage sources, each of which may be varied to generate a voltage signal of a particular value, and multiple inverters, each of which is configured to receive either a clock signal or its complement signal and one of the voltage signals. Based on these inputs, each inverter generates a control signal that is delivered to a corresponding switch in the input stage of the chopper operational amplifier to control the gate voltage of that switch. Based on the difference between the values of the voltage signals, the current control circuit operates to reduce the amplitudes of base currents induced by charge injection at the input terminals of the chopper operational amplifier.
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公开(公告)号：US20220209730A1
公开(公告)日：2022-06-30
申请号：US17136073
申请日：2020-12-29
Applicant: Texas Instruments Incorporated
Inventor： Vadim Valerievich Ivanov , Munaf Hussain Shaik , Srinivas Kumar Pulijala , Patrick Forster , Jerry Lee Doorenbos
Abstract: Disclosed is a system that comprises an operational amplifier with adjustable operational parameters and a trimming module. The trimming module can adjust the operational parameters of the op-amp based on a memory value to compensate for an offset voltage of the op-amp. The trimming module can comprise successive approximation register (SAR) logic that controls the memory value. The SAR logic can be configured to detect a given memory value that causes an output voltage of the op-amp to be within a predetermined voltage interval when applying a predetermined common mode voltage to inverting and non-inverting inputs of the op-amp.
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公开(公告)号：US11888447B2
公开(公告)日：2024-01-30
申请号：US17232985
申请日：2021-04-16
Applicant: Texas Instruments Incorporated
CPC classification number: H03F1/0233 , H03F3/45475 , H03F2200/462 , H03F2200/471 , H03F2200/504
Abstract: A circuit includes an operational amplifier having: a positive input; a negative input; an operational amplifier output; a differential front end; a positive channel (PCH) input stage; a negative channel (NCH) input stage; and an output stage. The operational amplifier also includes a current limit circuit coupled to an output of the output stage and including: an output current sense voltage circuit having an output configured to provide an output current sense voltage; an indirect current feedback circuit coupled to the output of the output current sense voltage circuit, the indirect current feedback circuit having an output configured to provide an output current feedback sense voltage responsive to the output current sense voltage; and control circuitry coupled to the indirect current feedback circuit and configured vary a resistance between the output stage output and ground responsive to a difference between the output current feedback sense voltage and a reference voltage.
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公开(公告)号：US20220360239A1
公开(公告)日：2022-11-10
申请号：US17307327
申请日：2021-05-04
Applicant: Texas Instruments Incorporated
Inventor： Vadim Valerievich Ivanov , Munaf Hussain Shaik , Srinivas Kumar Pulijala , Patrick Forster , Jerry Lee Doorenbos
Abstract: Disclosed is a system comprising a plurality of operational amplifiers, each operational amplifier having individually adjustable operational parameters, and a trimming circuit. The trimming circuit includes successive approximation register (SAR) logic that determines associated memory values. The trimming circuit changes the adjustable operational parameters of each operation amplifier based on the associated memory values.
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公开(公告)号：US20230092097A1
公开(公告)日：2023-03-23
申请号：US17482195
申请日：2021-09-22
Applicant: Texas Instruments Incorporated
Abstract: An example apparatus includes: a folded cascode circuit including a first input terminal, a second input terminal, a first output terminal, and a second output terminal; a first feedback loop including a third output terminal, the third output terminal coupled to the first output terminal; a second feedback loop including a fourth output terminal, the fourth output terminal coupled to the second output terminal; and a first driver including a first control terminal and a fifth output terminal, the first control terminal coupled to the third output terminal; and a second driver including a second control terminal and a sixth output terminal, the second control terminal coupled to the fourth output terminal, the sixth output terminal coupled to the fifth output terminal.
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Patent Agency Ranking
公开(公告)号：US20210242844A1
公开(公告)日：2021-08-05
申请号：US16777521
申请日：2020-01-30
Applicant: Texas Instruments Incorporated
Inventor： Vadim Valerievich Ivanov , Srinivas Kumar Pulijala
IPC: H03F3/45
Abstract: An apparatus has four transistors. The first and third transistors each have a gate coupled to a first input terminal and second input terminal respectively, a source coupled to a current source and to a first terminal of a bias voltage source, and a substrate coupled to a second terminal of the bias voltage source. The second and fourth transistors each have a gate coupled to the first input terminal and the second input terminal respectively, a source coupled to the drain of the first and third transistors respectively, a drain coupled to a lower voltage supply and a substrate coupled to its source. The bias voltage source increases the threshold voltages of the first and third transistors above the second and fourth transistors, respectively. This ensures that the first and third transistors turn on after the second and fourth transistors, respectively.
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公开(公告)号：US12068730B2
公开(公告)日：2024-08-20
申请号：US17307327
申请日：2021-05-04
Applicant: Texas Instruments Incorporated
Inventor： Vadim Valerievich Ivanov , Munaf Hussain Shaik , Srinivas Kumar Pulijala , Patrick Forster , Jerry Lee Doorenbos
CPC classification number: H03F3/45475 , H03M1/38 , H03M1/66 , H03F3/211 , H03F2200/129
Abstract: Disclosed is a system comprising a plurality of operational amplifiers, each operational amplifier having individually adjustable operational parameters, and a trimming circuit. The trimming circuit includes successive approximation register (SAR) logic that determines associated memory values. The trimming circuit changes the adjustable operational parameters of each operation amplifier based on the associated memory values.
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公开(公告)号：US20230034632A1
公开(公告)日：2023-02-02
申请号：US17386979
申请日：2021-07-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Vadim Valerievich Ivanov , Srinivas Kumar Pulijala
Abstract: Differential input circuits employ protection transistors and feedback paths to limit the differential voltage applied to input transistors. In an example arrangement, a differential input voltage is applied to terminals of the protection transistors, and current paths couple the respective protection transistors to control terminals of the input transistors, respectively. A control terminal drive voltage source is coupled to the control terminals of the input protection transistors to control the drive voltage applied to those terminals. Feedback paths, one for each of the input transistors, control voltages applied to the control terminals of the input transistors, maintaining the input differential voltage at a relatively low level and defined by the product of a specified current value and a specified resistance value.
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公开(公告)号：US11251759B2
公开(公告)日：2022-02-15
申请号：US16777521
申请日：2020-01-30
Applicant: Texas Instruments Incorporated
Inventor： Vadim Valerievich Ivanov , Srinivas Kumar Pulijala
IPC: H03F3/45
Abstract: An apparatus has four transistors. The first and third transistors each have a gate coupled to a first input terminal and second input terminal respectively, a source coupled to a current source and to a first terminal of a bias voltage source, and a substrate coupled to a second terminal of the bias voltage source. The second and fourth transistors each have a gate coupled to the first input terminal and the second input terminal respectively, a source coupled to the drain of the first and third transistors respectively, a drain coupled to a lower voltage supply and a substrate coupled to its source. The bias voltage source increases the threshold voltages of the first and third transistors above the second and fourth transistors, respectively. This ensures that the first and third transistors turn on after the second and fourth transistors, respectively.
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公开(公告)号：US11881825B2
公开(公告)日：2024-01-23
申请号：US17136073
申请日：2020-12-29
Applicant: Texas Instruments Incorporated
Inventor： Vadim Valerievich Ivanov , Munaf Hussain Shaik , Srinivas Kumar Pulijala , Patrick Forster , Jerry Lee Doorenbos
CPC classification number: H03F3/45475 , H03M1/38 , H03M1/66 , H03F2200/375
Abstract: Disclosed is a system that comprises an operational amplifier with adjustable operational parameters and a trimming module. The trimming module can adjust the operational parameters of the op-amp based on a memory value to compensate for an offset voltage of the op-amp. The trimming module can comprise successive approximation register (SAR) logic that controls the memory value. The SAR logic can be configured to detect a given memory value that causes an output voltage of the op-amp to be within a predetermined voltage interval when applying a predetermined common mode voltage to inverting and non-inverting inputs of the op-amp.
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