-
公开(公告)号：US20180068894A1
公开(公告)日：2018-03-08
申请号：US15343557
申请日：2016-11-04
摘要： An example integrated circuit die includes: a plurality of lower level conductor layers, a plurality of lower level insulator layers between the plurality of lower level conductor layers, a plurality of lower level vias extending vertically through the lower level insulator layers, a plurality of upper level conductor layers overlying the lower level conductor layers, a plurality of upper level insulator layers between and surrounding the upper level conductor layers, a plurality of upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.
-
2.发明授权公开(公告)号：US09100035B2
公开(公告)日：2015-08-04
申请号：US14194208
申请日：2014-02-28
发明人： Udayan Dasgupta , Abhijit A. Patki , Ganesan Thiagarajan , Janakiraman S , Madhulatha Bonu , Venugopal Gopinathan
CPC分类号： H03M1/125 , H03M1/08 , H03M1/0836 , H03M1/0845 , H03M1/0854 , H03M1/089 , H03M1/124 , H03M1/1265 , H03M1/186 , H03M1/36
摘要： A snapout calculator, and wherein the snapout calculator determines where the reference levels for the various comparators shall be placed after each asynchronous sample is generated.
摘要翻译： 跳槽计算器，并且其中，所述卡扣计算器确定在每个异步样本产生之后将放置各种比较器的参考电平。
-
公开(公告)号：US20140247176A1
公开(公告)日：2014-09-04
申请号：US14194304
申请日：2014-02-28
发明人： Janakiraman S , Udayan Dasgupta , Ganesan Thiagarajan , Abhijit A. Patki , Madhulatha Bonu , Venugopal Gopinathan
IPC分类号： H03M1/18
CPC分类号： H03M1/125 , H03M1/08 , H03M1/0836 , H03M1/0845 , H03M1/0854 , H03M1/089 , H03M1/124 , H03M1/1265 , H03M1/186 , H03M1/36
摘要： An apparatus, comprising: an analog to digital converter including: a clipping detector; and a post-processor, wherein the post processor generates synchronous values of clipped data based on non-clipped values of non-clipped data.
摘要翻译： 一种装置，包括：模数转换器，包括：限幅检测器; 以及后处理器，其中所述后处理器基于未剪切数据的未剪切值来生成剪切数据的同步值。
-
公开(公告)号：US10547352B2
公开(公告)日：2020-01-28
申请号：US15454797
申请日：2017-03-09
摘要： In described examples, a first die includes a primary LC tank oscillator having a natural frequency of oscillation to induce a forced oscillation in a secondary LC tank oscillator of a separate second die via a magnetic coupling between the primary LC tank oscillator and the secondary LC tank oscillator.
-
公开(公告)号：US10546780B2
公开(公告)日：2020-01-28
申请号：US15343557
申请日：2016-11-04
IPC分类号： H01L21/78 , H01L23/18 , H01L29/06 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/00 , H01L49/02
摘要： An example integrated circuit die includes: a plurality of lower level conductor layers, a plurality of lower level insulator layers between the plurality of lower level conductor layers, a plurality of lower level vias extending vertically through the lower level insulator layers, a plurality of upper level conductor layers overlying the lower level conductor layers, a plurality of upper level insulator layers between and surrounding the upper level conductor layers, a plurality of upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.
-
6.发明授权公开(公告)号：US08988266B2
公开(公告)日：2015-03-24
申请号：US14194181
申请日：2014-02-28
发明人： Janakiraman S , Udayan Dasgupta , Ganesan Thiagarajan , Abhijit A. Patki , Madhulatha Bonu , Venugopal Gopinathan
CPC分类号： H03M1/125 , H03M1/08 , H03M1/0836 , H03M1/0845 , H03M1/0854 , H03M1/089 , H03M1/124 , H03M1/1265 , H03M1/186 , H03M1/36
摘要： A method, comprising: receiving an analog input; determining an upper outer rail and a lower outer rail as polling values to be used by voltage comparators; blanking at least three comparators; determining which two of the at least three comparators are closest to the input analog voltage levels; defining the two comparators which are closest to the analog input signal to be the next comparators of the next sampling process; assigning a remaining comparator at a voltage level in between the new top and bottom voltage levels; enabling the outer rails, but blanking the inner rail; progressively narrowing down the voltage range spanned by the two outer comparators; and generating a 2-tuple value of an asynchronous voltage comparator crossing.
摘要翻译： 一种方法，包括：接收模拟输入; 确定上部外轨道和下部外部轨道作为要由电压比较器使用的轮询值; 至少阻止三位比较人; 确定所述至少三个比较器中的哪两个最接近所述输入模拟电压电平; 将最接近模拟输入信号的两个比较器定义为下一个采样过程的下一个比较器; 将剩余比较器分配在新的顶部和底部电压电平之间的电压电平; 使得外轨能够消除内轨; 逐渐缩小两个外部比较器跨越的电压范围; 并产生异步电压比较器杂交的2元组值。
-
7.发明申请公开(公告)号：US20140247175A1
公开(公告)日：2014-09-04
申请号：US14194281
申请日：2014-02-28
发明人： Udayan Dasgupta , Janakiraman S , Ganesan Thiagarajan , Abhijit A. Patki , Madhulatha Bonu , Venugopal Gopinathan
CPC分类号： H03M1/125 , H03M1/08 , H03M1/0836 , H03M1/0845 , H03M1/0854 , H03M1/089 , H03M1/124 , H03M1/1265 , H03M1/186 , H03M1/36
摘要： A method, comprising: receiving a plurality of 2-tuples of asynchronously sampled inputs at an asynchronous to synchronous reconstructor; performing a coarse asynchronous to synchronous conversion using the plurality of 2-tuples to generate a plurality of low precision synchronous outputs; generating a high precision synchronous output, z0, using a plurality of asynchronous 2-tuples, low precision synchronous outputs after it, and its own high precision outputs from previous steps; calculating c0 and c−1 by summing future low precision outputs and the past high precision outputs after they are weighted with the appropriate windowed sinc. values and then subtracted from appropriate asynchronous samples; calculating, the four quantities “s−11”, “s01”, “s00” and “s−10” based on particular values of the windowed sinc. function; and using c0, c−1, s−11, s01, s00 and s−10, the high precision synchronous output of interest, z0 is generated.
摘要翻译： 一种方法，包括：在异步同步重构器处接收多个异步采样输入的2元组; 使用所述多个2元组执行粗略的异步到同步转换，以产生多个低精度同步输出; 使用多个异步2元组，其后的低精度同步输出以及自己的高精度输出从前面的步骤产生高精度同步输出z0; 通过将未来的低精度输出和过去的高精度输出相加后，使用适当的加窗sinc来计算c0和c-1。 值，然后从适当的异步采样中减去; 基于窗口的sinc的特定值计算四个量“s-11”，“s01”，“s00”和“s-10”。 功能; 并使用c0，c-1，s-11，s01，s00和s-10，生成高精度的同步输出z0。
-
8.发明申请公开(公告)号：US20140247171A1
公开(公告)日：2014-09-04
申请号：US14194181
申请日：2014-02-28
发明人： Janakiraman S. , Udayan Dasgupta , Ganesan Thiagarajan , Abhijit A. Patki , Madhulatha Bonu , Venugopal Gopinathan
CPC分类号： H03M1/125 , H03M1/08 , H03M1/0836 , H03M1/0845 , H03M1/0854 , H03M1/089 , H03M1/124 , H03M1/1265 , H03M1/186 , H03M1/36
摘要： A method, comprising: receiving an analog input; determining an upper outer rail and a lower outer rail as polling values to be used by voltage comparators; blanking at least three comparators; determining which two of the at least three comparators are closest to the input analog voltage levels; defining the two comparators which are closest to the analog input signal to be the next comparators of the next sampling process; assigning a remaining comparator at a voltage level in between the new top and bottom voltage levels; enabling the outer rails, but blanking the inner rail; progressively narrowing down the voltage range spanned by the two outer comparators; and generating a 2-tuple value of an asynchronous voltage comparator crossing.
摘要翻译： 一种方法，包括：接收模拟输入; 确定上部外轨道和下部外部轨道作为要由电压比较器使用的轮询值; 至少阻止三位比较人; 确定所述至少三个比较器中的哪两个最接近所述输入模拟电压电平; 将最接近模拟输入信号的两个比较器定义为下一个采样过程的下一个比较器; 将剩余比较器分配在新的顶部和底部电压电平之间的电压电平; 使得外轨能够消除内轨; 逐渐缩小两个外部比较器跨越的电压范围; 并产生异步电压比较器杂交的2元组值。
-
公开(公告)号：US20140357186A1
公开(公告)日：2014-12-04
申请号：US14289895
申请日：2014-05-29
IPC分类号： H04B5/00
CPC分类号： H04B5/0093 , H01L23/645 , H01L23/66 , H01L2223/6677 , H03B5/08 , H04B5/0075
摘要： In apparatus for die-to-die communication, a first die includes at least a first circuit, and a second die includes at least a second circuit. The first die is separated by a fixed distance from the second die. In response to a signal, the first circuit is configured to induce a current in the second circuit via a magnetic coupling between the first circuit and the second circuit.
摘要翻译： 在管芯到管芯通信的装置中，第一管芯至少包括第一电路，第二管芯至少包括第二电路。 第一模具与第二模具分开一定距离。 响应于信号，第一电路被配置为通过第一电路和第二电路之间的磁耦合在第二电路中感应电流。
-
公开(公告)号：US11515209B2
公开(公告)日：2022-11-29
申请号：US16773692
申请日：2020-01-27
IPC分类号： H01L21/78 , H01L23/58 , H01L23/66 , H01L23/18 , H01L29/06 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/00 , H01L49/02
摘要： An example integrated circuit die includes: lower level conductor layers, lower level insulator layers between the lower level conductor layers, lower level vias extending vertically through the lower level insulator layers, upper level conductor layers overlying the lower level conductor layers, upper level insulator layers between and surrounding the upper level conductor layers, upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.
-
-
-
-
-
-
-
-
-
搜索结果
18 条记录 (耗时 0.016 秒)
