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    Multirow gull-wing package for microelectronic devices
    2.
    发明授权
    Multirow gull-wing package for microelectronic devices 有权

    公开(公告)号：US11335570B2

    公开(公告)日：2022-05-17

    申请号：US16225182

    申请日：2018-12-19

    Applicant: Texas Instruments Incorporated

    Inventor： Sreenivasan K Koduri

    IPC: H01L23/498 ,  H01L23/495 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

    Abstract: A microelectronic device, in a multirow gull-wing chip scale package, has a die connected to intermediate pads by wire bonds. The intermediate pads are free of photolithographically-defined structures. An encapsulation material at least partially surrounds the die and the wire bonds, and contacts the intermediate pads. Inner gull-wing leads and outer gull-wing leads, located outside of the encapsulation material, are attached to the intermediate pads. The gull-wing leads have external attachment surfaces opposite from the intermediate pads. The external attachment surfaces of the outer gull-wing leads are located outside of the external attachment surfaces of the inner gull-wing leads. The microelectronic device is formed by mounting the die on a carrier, forming the intermediate pads without using a photolithographic process, and forming the wire bonds. The encapsulation material is formed, and the carrier is subsequently removed, exposing the intermediate pads. The gull-wing leads are formed on the intermediate pads.

    Integrated circuit package with current sense element
    3.
    发明授权
    Integrated circuit package with current sense element 有权

    公开(公告)号：US12066459B2

    公开(公告)日：2024-08-20

    申请号：US17364477

    申请日：2021-06-30

    Applicant: Texas Instruments Incorporated

    Inventor： Robert Allan Neidorff ,  Sreenivasan K Koduri

    IPC: G01R1/067 ,  G01R31/28 ,  H01L23/495

    CPC classification number: G01R1/06711 ,  G01R31/2851 ,  H01L23/4952

    Abstract: A semiconductor device includes a leadframe having a first level and a second level. The semiconductor device includes a semiconductor die and a conductive alloy. The conductive alloy is between the semiconductor die and the first level of the lead frame. The conductive alloy is configured to be a current sense element. The semiconductor device further includes a first conductive post coupling the semiconductor die to the conductive alloy, a second conductive post coupling the semiconductor die to the conductive alloy, and a third conductive post coupling the semiconductor die to the second level of the lead frame. The second conductive post is configured to be a first sense terminal. The third conductive post is configured to be a second sense terminal.

    LOW COST RELIABLE FAN-OUT FAN-IN CHIP SCALE PACKAGE
    4.
    发明申请
    LOW COST RELIABLE FAN-OUT FAN-IN CHIP SCALE PACKAGE 有权

    公开(公告)号：US20220392817A1

    公开(公告)日：2022-12-08

    申请号：US17888263

    申请日：2022-08-15

    Applicant: Texas Instruments Incorporated

    Inventor： Sreenivasan K Koduri

    IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

    Abstract: A microelectronic device, in a fan-out fan-in chip scale package, has a die and an encapsulation material at least partially surrounding the die. Fan-out connections from the die extend through the encapsulation material and terminate adjacent to the die. The fan-out connections include wire bonds, and are free of photolithographically-defined structures. Fan-in/out traces connect the fan-out connections to bump bond pads. The die and at least a portion of the bump bond pads partially overlap each other. The microelectronic device is formed by mounting the die on a carrier, and forming the fan-out connections, including the wire bonds, without using a photolithographic process. The die and the fan-out connections are covered with an encapsulation material, and the carrier is subsequently removed, exposing the fan-out connections. The fan-in/out traces are formed so as to connect to the exposed portions of the fan-out connections, and extend to the bump bond pads.

    Wafer level bump stack for chip scale package
    5.
    发明授权
    Wafer level bump stack for chip scale package 有权

    公开(公告)号：US11064615B2

    公开(公告)日：2021-07-13

    申请号：US16588220

    申请日：2019-09-30

    Applicant: Texas Instruments Incorporated

    Inventor： Sreenivasan K Koduri

    IPC: H05K3/34 ,  H05K1/02 ,  H05K3/28 ,  H05K3/38

    Abstract: A microelectronic device includes a die less than 300 microns thick, and an interface tile. Die attach leads on the interface tile are electrically coupled to die terminals on the die through interface bonds. The microelectronic device includes an interposer between the die and the interface tile. Lateral perimeters of the die, the interposer, and the interface tile are aligned with each other. The microelectronic device may be formed by forming the interface bonds and an interposer layer, while the die is part of a wafer and the interface tile is part of an interface lamina. Kerfs are formed through the interface lamina, through the interposer, and partway through the wafer, around a lateral perimeter of the die. Material is subsequently removed at a back surface of the die to the kerfs, so that a thickness of the die is less than 300 microns.

    WAFER LEVEL BUMP STACK FOR CHIP SCALE PACKAGE
    7.
    发明申请
    WAFER LEVEL BUMP STACK FOR CHIP SCALE PACKAGE 有权

    公开(公告)号：US20210345495A1

    公开(公告)日：2021-11-04

    申请号：US17374946

    申请日：2021-07-13

    Applicant: Texas Instruments Incorporated

    Inventor： Sreenivasan K Koduri

    IPC: H05K3/34 ,  H05K1/02 ,  H05K3/28 ,  H05K3/38

    Abstract: A microelectronic device includes a die less than 300 microns thick, and an interface tile. Die attach leads on the interface tile are electrically coupled to die terminals on the die through interface bonds. The microelectronic device includes an interposer between the die and the interface tile. Lateral perimeters of the die, the interposer, and the interface tile are aligned with each other. The microelectronic device may be formed by forming the interface bonds and an interposer layer, while the die is part of a wafer and the interface tile is part of an interface lamina. Kerfs are formed through the interface lamina, through the interposer, and partway through the wafer, around a lateral perimeter of the die. Material is subsequently removed at a back surface of the die to the kerfs, so that a thickness of the die is less than 300 microns.

    Thermometer device and method of making
    8.
    发明授权
    Thermometer device and method of making 有权

    公开(公告)号：US10330537B2

    公开(公告)日：2019-06-25

    申请号：US15495200

    申请日：2017-04-24

    Applicant: Texas Instruments Incorporated

    Inventor： Sreenivasan K Koduri

    IPC: G01K1/18 ,  G01K13/00 ,  G01K1/14 ,  A61B5/01

    Abstract: A method of manufacturing a thermometer probe includes: obtaining a hollow housing having an open end and a curved inner surface; obtaining a flexible detecting component having an adhesive layer; obtaining an insertion component; detachably attaching the flexible detecting component to the insertion component; inserting the insertion component, having the flexible detecting component attached thereto, through the open end of the hollow housing and into the hollow housing such that the adhesive layer is disposed between the insertion component and the inner surface; and adhering, via the adhesive layer, the flexible detecting component to the curved inner surface.

    INDUCTOR ON MICROELECTRONIC DIE
    9.
    发明公开
    INDUCTOR ON MICROELECTRONIC DIE 审中-公开

    公开(公告)号：US20230253443A1

    公开(公告)日：2023-08-10

    申请号：US18301314

    申请日：2023-04-17

    Applicant: Texas Instruments Incorporated

    Inventor： Sreenivasan K Koduri

    IPC: H01L27/08 ,  H01L23/00

    CPC classification number: H01L28/10 ,  H01L24/13 ,  H01L2924/19104 ,  H01L2924/19042

    Abstract: A microelectronic device has bump bonds and an inductor on a die. The microelectronic device includes first lateral conductors extending along a terminal surface of the die, wherein at least some of the first lateral conductors contact at least some of terminals of the die. The microelectronic device also includes conductive columns on the first lateral conductors, extending perpendicularly from the terminal surface, and second lateral conductors on the conductive columns, opposite from the first lateral conductors, extending laterally in a plane parallel to the terminal surface. A first set of the first lateral conductors, the conductive columns, and the second lateral conductors provide the bump bonds of the microelectronic device. A second set of the first lateral conductors, the conductive columns, and the second lateral conductors are electrically coupled in series to form the inductor. Methods of forming the microelectronic device are also disclosed.

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