公开(公告)号：US20230170282A1

公开(公告)日：2023-06-01

申请号：US17537923

申请日：2021-11-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yuntao Xu ,  Min Hui Ma ,  Tiange Xie ,  Rongwei Zhang

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49513 ,  H01L24/32 ,  H01L24/73 ,  H01L23/3121 ,  H01L23/49541 ,  H01L24/83 ,  H01L21/56 ,  H01L2224/32245 ,  H01L2224/32013 ,  H01L2224/73265 ,  H01L2224/8385

Abstract: A semiconductor device includes a silicon die having a first side and a second side, an adhesive layer attached to the first side of the silicon die, and a lead frame. The lead frame comprises a die attach pad having a mounting surface. The mounting surface has a smaller area than an area of the adhesive layer. The silicon die is mounted on the lead frame at the mounting surface so that edges of the silicon die and the adhesive layer overhang the die attach pad without touching the die attach pad. The semiconductor device further includes one or more leads that are spaced apart from the edges of the silicon die and the adhesive layer.

公开(公告)号：US20240258215A1

公开(公告)日：2024-08-01

申请号：US18162079

申请日：2023-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mei Jiao ,  Huo Yun Duan ,  Zi Qi Wang ,  Tiange Xie

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L2924/181

Abstract: An example apparatus includes: a metal leadframe including a die pad in a central portion and leads spaced from the die pad. The leads include: an interior end spaced from the die pad and having a full thickness of the metal leadframe; a central portion connected to the interior end and extending away from the die pad having a partial thickness less than the full thickness; and an exterior end having the full thickness extending from the central portion. A semiconductor die is mounted to the die pad by die attach material. Wire bonds couple bond pads of the semiconductor die to the interior ends of the leads. Mold compound covers the semiconductor die, the die pad, the wire bonds, the interior ends of the leads, the central portion of the leads, and portions of the exterior ends of the leads to form a semiconductor device package.

公开(公告)号：US20230197579A1

公开(公告)日：2023-06-22

申请号：US17750270

申请日：2022-05-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xingfang Ma ,  Juan Herbsommer ,  Tiange Xie ,  Alex Chin Sern Ting

IPC: H01L23/495 ,  H01L23/31

CPC classification number: H01L23/49548 ,  H01L23/3107 ,  H01L23/49503

Abstract: An integrated circuit package includes a first die attach pad (DAP) having a first bottom surface, a first semiconductor die attached to the first DAP, a second DAP having a second bottom surface, wherein the first bottom surface and the second bottom surface are coplanar, and a second semiconductor die attached to the second DAP. A nonlinear DAP linking structure couples the first DAP to the second DAP, wherein the DAP linking structure does not include any direct linear connections between the first DAP and the second DAP. The nonlinear DAP linking structure is configured to deform without causing the first DAP and the second DAP to become non-coplanar. A mold compound covers the first and second DAPs, the first and second semiconductor dies, and the nonlinear DAP linking structure.

公开(公告)号：US12224181B2

公开(公告)日：2025-02-11

申请号：US17458653

申请日：2021-08-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Tiange Xie ,  Li Xiang Zheng ,  Alex Chin Sern Ting ,  Zhenzhen He

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/495

Abstract: One example described herein includes a method for fabricating integrated circuit (IC) packages. The method includes fabricating a plurality of IC dies and providing a conductive metal material sheet. The method also includes laser-cutting the conductive metal material sheet to form a lead-frame sheet. The lead-frame sheet includes at least one of through-holes and three-dimensional locking features. The method further includes coupling the IC dies to the lead-frame sheet and coupling the lead-frame sheet and the IC dies to packaging material to form an IC package block comprising the IC packages.