公开(公告)号：US20210265246A1

公开(公告)日：2021-08-26

申请号：US17318974

申请日：2021-05-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Tianyi Luo ,  Jonathan Almeria Noquil ,  Osvaldo Jorge Lopez

IPC: H01L23/495 ,  H01L25/07 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

Abstract: A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.

公开(公告)号：US20240224415A1

公开(公告)日：2024-07-04

申请号：US18603099

申请日：2024-03-12

Applicant: Texas Instruments Incorporated

Inventor： Tianyi Luo ,  Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Satyendra Singh Chauhan ,  Bernardo Gallegos

IPC: H05K1/02 ,  H01L21/50 ,  H01L21/60 ,  H01L23/00 ,  H01L23/538

CPC classification number: H05K1/0271 ,  H01L21/50 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/14 ,  H01L2021/60097 ,  H01L2224/16225

Abstract: In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.

公开(公告)号：US11817375B2

公开(公告)日：2023-11-14

申请号：US16274562

申请日：2019-02-13

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Tianyi Luo ,  Jonathan Almeria Noquil

IPC: H01L23/49 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49541 ,  H01L21/4828 ,  H01L21/56 ,  H01L23/3135 ,  H01L23/49582

Abstract: A method of making a semiconductor device includes separating a conductive structure of a leadframe into interior conductive leads using an etching process. The method includes forming a first molded structure by applying a first molding compound to a leadframe having a conductive structure, separating the conductive structure into at least two interior contact portions, attaching a semiconductor die to at least one of the interior contact portions, the at least two interior contact portions being supported by the first molding compound, and forming a second molded structure by applying a second molding compound to at least part of the semiconductor die and at least two interior contact portions.

公开(公告)号：US11658130B2

公开(公告)日：2023-05-23

申请号：US17138981

申请日：2020-12-31

Applicant: Texas Instruments Incorporated

Inventor： Tianyi Luo ,  Jonathan Almeria Noquil ,  Satyendra Singh Chauhan ,  Osvaldo Jorge Lopez ,  Lance Cole Wright

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49513 ,  H01L23/49562 ,  H01L23/49575

Abstract: A packaged electronic device includes a semiconductor die, a conductive plate coupled to a lead, a solder structure and a package structure. The semiconductor die has opposite first and second sides and a terminal exposed along the second side. The conductive plate has opposite first and second sides and an indent that extends into the first side, the conductive plate, and the solder structure extends between the second side of the semiconductor die and the first side of the conductive plate to electrically couple the conductive plate to the terminal, and the solder structure extends into the indent. The package structure encloses the semiconductor die, the conductive plate and a portion of the lead.

公开(公告)号：US20200258822A1

公开(公告)日：2020-08-13

申请号：US16274562

申请日：2019-02-13

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Tianyi Luo ,  Jonathan Almeria Noquil

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A method of making a semiconductor device includes separating a conductive structure of a leadframe into interior conductive leads using an etching process. The method includes forming a first molded structure by applying a first molding compound to a leadframe having a conductive structure, separating the conductive structure into at least two interior contact portions, attaching a semiconductor die to at least one of the interior contact portions, the at least two interior contact portions being supported by the first molding compound, and forming a second molded structure by applying a second molding compound to at least part of the semiconductor die and at least two interior contact portions.

公开(公告)号：US12243849B2

公开(公告)日：2025-03-04

申请号：US17491378

申请日：2021-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chittranjan Mohan Gupta ,  Yiqi Tang ,  Rajen Manicon Murugan ,  Jie Chen ,  Tianyi Luo

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

Abstract: In examples, a semiconductor package comprises a substrate and multiple columns of semiconductor dies positioned approximately in parallel along a length of the substrate. The package also includes multiple passive components positioned between the multiple columns of semiconductor dies, the multiple passive components angled between 30 and 60 degrees relative to the length of the substrate, a pair of the multiple passive components having a gap therebetween that is configured to permit mold compound flow through capillary action. The package also includes a mold compound covering the substrate, the multiple columns of semiconductor dies, and the multiple passive components.

公开(公告)号：US12176274B2

公开(公告)日：2024-12-24

申请号：US16200278

申请日：2018-11-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonathan Almeria Noquil ,  Osvaldo Jorge Lopez ,  Tianyi Luo

IPC: H01L23/495 ,  H01L23/373 ,  H01L23/40 ,  H01L25/065

Abstract: A semiconductor package comprises a first die thermally coupled to a first thermally conductive device. The first thermally conductive device has a first surface exposed to an exterior of the semiconductor package. The package comprises a second die thermally coupled to a second thermally conductive device, the second thermally conductive device having a second surface exposed to an exterior of the semiconductor package. The first and second dies are positioned in different horizontal planes.

公开(公告)号：US11930590B2

公开(公告)日：2024-03-12

申请号：US17218792

申请日：2021-03-31

Applicant: Texas Instruments Incorporated

Inventor： Tianyi Luo ,  Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Satyendra Singh Chauhan ,  Bernardo Gallegos

IPC: H05K1/02 ,  H01L21/50 ,  H01L23/00 ,  H01L23/538 ,  H01L21/60

CPC classification number: H05K1/0271 ,  H01L21/50 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/14 ,  H01L2021/60097 ,  H01L2224/16225

Abstract: In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.

公开(公告)号：US11640932B2

公开(公告)日：2023-05-02

申请号：US17318974

申请日：2021-05-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Tianyi Luo ,  Jonathan Almeria Noquil ,  Osvaldo Jorge Lopez

IPC: H01L23/495 ,  H01L25/07 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

Abstract: A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.

公开(公告)号：US20220210911A1

公开(公告)日：2022-06-30

申请号：US17218792

申请日：2021-03-31

Applicant: Texas Instruments Incorporated

Inventor： Tianyi Luo ,  Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Satyendra Singh Chauhan ,  Bernardo Gallegos

IPC: H05K1/02 ,  H01L23/00 ,  H01L23/538 ,  H01L21/50

Abstract: In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.