公开(公告)号：US20190006384A1

公开(公告)日：2019-01-03

申请号：US15909432

申请日：2018-03-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Taichi IWASAKI ,  Takeshi SONEHARA ,  Hiroyuki NITTA

IPC: H01L27/11582 ,  H01L23/58 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11573 ,  H01L23/00

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/26513 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/32053 ,  H01L21/32055 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/78 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/1037 ,  H01L29/7883 ,  H01L29/7889 ,  H01L29/7926

Abstract: A semiconductor memory device includes a semiconductor layer having a termination region surrounding a device region, the termination region including a first stacked body having a first, insulating, layer located on a surface of the substrate, a second, conductive, layer located over the first layer, and a third, insulating, layer located over the second layer, an opening extending through the first stacked body, a fourth, insulating, layer located in the opening in the first stacked body and over the surface of the semiconductor substrate in the opening, a fifth, insulating, layer, located over the fourth layer, and a wall surrounding the device region, the wall extending inwardly of the opening and contacting one of the surface of the semiconductor substrate or a nitride material on the surface of the substrate, wherein the composition of the third and fifth layers is different from that of the first and third layers.